S9S12G128F0CLF Datasheet, PDF (278/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

S12S Debug Module (S12SDBG)
8.1.5 Block Diagram
TAGHITS
SECURE
CPU BUS
COMPARATOR A
COMPARATOR B
COMPARATOR C
MATCH0
MATCH1
MATCH2
TAGS
BREAKPOINT REQUESTS
TO CPU
TRANSITION
TAG &
MATCH
CONTROL
LOGIC
STATE
STATE
STATE SEQUENCER
TRACE
CONTROL
TRIGGER
READ TRACE DATA (DBG READ DATA BUS)
Figure 8-1. Debug Module Block Diagram
8.2 External Signal Description
There are no external signals associated with this module.
8.3 Memory Map and Registers
TRACE BUFFER
8.3.1 Module Memory Map
A summary of the registers associated with the DBG sub-block is shown in Figure 8-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
Address Name
Bit 7
6
5
R
0
0
0x0020 DBGC1
ARM
W
TRIG
R ¹TBF
0
0
0x0021 DBGSR
W
R
0
0
0x0022 DBGTCR
TSOURCE
W
R
0
0
0
0x0023 DBGC2
W
4
BDM
0
3
DBGBRK
0
2
0
SSF2
0
TRCMOD
0
0
0
1
Bit 0
COMRV
SSF1
SSF0
0
TALIGN
ABCM
Figure 8-2. Quick Reference to DBG Registers
MC9S12G Family Reference Manual, Rev.1.10
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Freescale Semiconductor