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S9S12G128F0CLF Datasheet, PDF (490/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual | |||
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Freescaleâs Scalable Controller Area Network (S12MSCANV3)
Table 16-11. CANRFLG Register Field Descriptions (continued)
Field
Description
1
OVRIF
Overrun Interrupt Flag â This ï¬ag is set when a data overrun condition occurs. If not masked, an error interrupt
is pending while this ï¬ag is set.
0 No data overrun condition
1 A data overrun detected
0
RXF2
Receive Buffer Full Flag â RXF is set by the MSCAN when a new message is shifted in the receiver FIFO.
This ï¬ag indicates whether the shifted buffer is loaded with a correctly received message (matching identiï¬er,
matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message
from the RxFG buffer in the receiver FIFO, the RXF ï¬ag must be cleared to release the buffer. A set RXF ï¬ag
prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt
is pending while this ï¬ag is set.
0 No new message available within the RxFG
1 The receiver FIFO is not empty. A new message is available in the RxFG
1 Redundant Information for the most critical CAN bus status which is âbus-offâ. This only occurs if the Tx error counter exceeds
a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state
skips to RxOK too. Refer also to TSTAT[1:0] coding in this register.
2 To ensure data integrity, do not read the receive buffer registers while the RXF ï¬ag is cleared. For MCUs with dual CPUs,
reading the receive buffer registers while the RXF ï¬ag is cleared may result in a CPU fault condition.
16.3.2.6 MSCAN Receiver Interrupt Enable Register (CANRIER)
This register contains the interrupt enable bits for the interrupt ï¬ags described in the CANRFLG register.
Module Base + 0x0005
Access: User read/write1
7
R
WUPIE
W
6
CSCIE
5
4
3
2
RSTATE1 RSTATE0 TSTATE1 TSTATE0
1
OVRIE
Reset:
0
0
0
0
0
0
0
Figure 16-9. MSCAN Receiver Interrupt Enable Register (CANRIER)
1 Read: Anytime
Write: Anytime when not in initialization mode
0
RXFIE
0
NOTE
The CANRIER register is held in the reset state when the initialization mode
is active (INITRQ=1 and INITAK=1). This register is writable when not in
initialization mode (INITRQ=0 and INITAK=0).
The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization
mode.
MC9S12G Family Reference Manual, Rev.1.10
490
Freescale Semiconductor
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