S9S12G128F0CLF Datasheet, PDF (352/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

S12 Clock, Reset and Power Management Unit (S12CPMU)
Table 10-20. Selectable Autonomous Periodical Interrupt Periods (continued)
APICLK
APIR[15:0]
0
0004
0
0005
0
.....
0
FFFD
0
FFFE
0
FFFF
1
0000
1
0001
1
0002
1
0003
1
0004
1
0005
1
.....
1
FFFD
1
FFFE
1
FFFF
1 _{When fACLK is trimmed to 10KHz.}
Selected Period
1.0 ms¹
1.2 ms¹
.....
13106.8 ms¹
13107.0 ms¹
13107.2 ms¹
2 * Bus Clock period
4 * Bus Clock period
6 * Bus Clock period
8 * Bus Clock period
10 * Bus Clock period
12 * Bus Clock period
.....
131068 * Bus Clock period
131070 * Bus Clock period
131072 * Bus Clock period
10.3.2.17 Reserved Register CPMUTEST3
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in Special
Mode can alter the S12CPMU’s functionality.
0x02F6
7
R
0
W
Reset
0
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-22. Reserved Register (CPMUTEST3)
Read: Anytime
Write: Only in Special Mode
MC9S12G Family Reference Manual, Rev.1.10
352
1
0
0
0
0
0
Freescale Semiconductor