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S9S12G128F0CLF Datasheet, PDF (276/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual | |||
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S12S Debug Module (S12SDBG)
BDM: Background Debug Mode
S12SBDM: Background Debug Module
DUG: Device User Guide, describing the features of the device into which the DBG is integrated.
WORD: 16 bit data entity
Data Line: 20 bit data entity
CPU: S12SCPU module
DBG: S12SDBG module
POR: Power On Reset
Tag: Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches
the execution stage a tag hit occurs.
8.1.2 Overview
The comparators monitor the bus activity of the CPU module. A match can initiate a state sequencer
transition. On a transition to the Final State, bus tracing is triggered and/or a breakpoint can be generated.
Independent of comparator matches a transition to Final State with associated tracing and breakpoint can
be triggered immediately by writing to the TRIG control bit.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads. Tracing is disabled when the MCU system is secured.
8.1.3 Features
⢠Three comparators (A, B and C)
â Comparators A compares the full address bus and full 16-bit data bus
â Comparator A features a data bus mask register
â Comparators B and C compare the full address bus only
â Each comparator features selection of read or write access cycles
â Comparator B allows selection of byte or word access cycles
â Comparator matches can initiate state sequencer transitions
⢠Three comparator modes
â Simple address/data comparator match mode
â Inside address range mode, Addmin ⤠Address ⤠Addmax
â Outside address range match mode, Address < Addmin or Address > Addmax
⢠Two types of matches
â Tagged â This matches just before a speciï¬c instruction begins execution
â Force â This is valid on the ï¬rst instruction boundary after a match occurs
⢠Two types of breakpoints
MC9S12G Family Reference Manual, Rev.1.10
276
Freescale Semiconductor
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