S9S12G128F0CLF Datasheet, PDF (285/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

S12S Debug Module (S12SDBG)
Table 8-12. CNT Decoding Table
TBF
CNT[5:0]
0
000001
000010
000100
000110
..
111111
1
000000
1
000001
..
..
111110
Description
1 line valid
2 lines valid
4 lines valid
6 lines valid
..
63 lines valid
64 lines valid; if using Begin trigger alignment,
ARM bit will be cleared and the tracing session ends.
64 lines valid,
oldest data has been overwritten by most recent data
8.3.2.7 Debug State Control Registers
There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if
transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the
next state for the state sequencer following a match. The three debug state control registers are located at
the same address in the register address map (0x0027). Each register can be accessed using the COMRV
bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register
(DBGMFR).
Table 8-13. State Control Register Access Encoding
COMRV
00
01
10
11
Visible State Control Register
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
8.3.2.7.1 Debug State Control Register 1 (DBGSCR1)
Address: 0x0027
7
R
0
W
Reset
0
6
5
4
3
2
1
0
0
0
0
SC3
SC2
SC1
SC0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-9. Debug State Control Register 1 (DBGSCR1)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the
targeted next state whilst in State1. The matches refer to the match channels of the comparator match
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
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