S9S12G128F0CLF Datasheet, PDF (645/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Table 20-18. PACTL Field Descriptions (continued)
Field
3:2
CLK[1:0]
1
PAOVI
0
PAI
Clock Select Bits — Refer to Table 20-20.
Pulse Accumulator Overflow Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAOVF is set.
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAIF is set.
Description
Timer Module (TIM16B8CV3)
Table 20-19. Pin Action
PAMOD
0
0
1
1
PEDGE
0
1
0
1
Pin Action
Falling edge
Rising edge
Div. by 64 clock enabled with pin high level
Div. by 64 clock enabled with pin low level
NOTE
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
because the ÷64 clock is generated by the timer prescaler.
Table 20-20. Timer Clock Selection
CLK1
0
0
1
1
CLK0
0
1
0
1
Timer Clock
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock frequency
For the description of PACLK please refer Figure 20-30.
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an
input clock to the timer counter. The change from one selected clock to the other happens immediately
after these bits are written.
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
645