S9S12G128F0CLF Datasheet, PDF (631/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Timer Module (TIM16B8CV3)
PULSE
ACCUMULATOR
PAD
CHANNEL 7 OUTPUT COMPARE
OCPD
TEN
TIOS7
Figure 20-4. Channel 7 Output Compare/Pulse Accumulator Logic
20.2 External Signal Description
The TIM16B8CV3 module has a selected number of external pins. Refer to device specification for exact
number.
20.2.1 IOC7 — Input Capture and Output Compare Channel 7
This pin serves as input capture or output compare for channel 7 if this channel is available. This can also
be configured as pulse accumulator input.
20.2.2 IOC6 - IOC0 — Input Capture and Output Compare Channel 6-0
Those pins serve as input capture or output compare for TIM168CV3 channel if the corresponding channel
is available.
NOTE
For the description of interrupts see Section 20.6, “Interrupts”.
20.3 Memory Map and Register Definition
This section provides a detailed description of all memory and registers.
20.3.1 Module Memory Map
The memory map for the TIM16B8CV3 module is given below in Figure 20-5. The address listed for each
register is the address offset. The total address for each register is the sum of the base address for the
TIM16B8CV3 module and the address offset for each register.
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
631