S9S12G128F0CLF Datasheet, PDF (335/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

S12 Clock, Reset and Power Management Unit (S12CPMU)
Table 10-2. Reference Clock Frequency Selection if OSC_LCP is enabled
REFCLK Frequency Ranges
(OSCE=1)
1MHz <= f_REF <= 2MHz
2MHz < f_REF <= 6MHz
6MHz < f_REF <= 12MHz
f_REF >12MHz
REFFRQ[1:0]
00
01
10
11
10.3.2.3 S12CPMU Post Divider Register (CPMUPOSTDIV)
The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK.
0x0036
7
6
5
4
3
2
1
0
R
0
0
0
W
POSTDIV[4:0]
Reset
0
0
0
0
0
0
1
1
= Unimplemented or Reserved
Figure 10-6. S12CPMU Post Divider Register (CPMUPOSTDIV)
Read: Anytime
Write: Anytime if PLLSEL=1. Else write has no effect.
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
f _PLL = ₍---_P----_O-----_S-^f--_T-^V---_D-^C----_I-^O-_V------₊-----₁---₎
f _PLL = ^f---^V----₄-^C----^O---
If PLL is selected (PLLSEL=1) f _bus = ^f---^P---₂-^L---^L--
10.3.2.4 S12CPMU Flags Register (CPMUFLG)
This register provides S12CPMU status bits and flags.
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
335