S9S12G128F0CLF Datasheet, PDF (292/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

S12S Debug Module (S12SDBG)
Table 8-23. Comparator Address Register Visibility
COMRV
00
01
10
11
Visible Comparator
DBGAAH, DBGAAM, DBGAAL
DBGBAH, DBGBAM, DBGBAL
DBGCAH, DBGCAM, DBGCAL
None
Read: Anytime. See Table 8-23 for visible register encoding.
Write: If DBG not armed. See Table 8-23 for visible register encoding.
Table 8-24. DBGXAH Field Descriptions
Field
Description
1–0
Bit[17:16]
Comparator Address High Compare Bits — The Comparator address high compare bits control whether the
selected comparator compares the address bus bits [17:16] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
8.3.2.8.3 Debug Comparator Address Mid Register (DBGXAM)
Address: 0x002A
R
W
Reset
7
Bit 15
0
6
Bit 14
0
5
Bit 13
0
4
Bit 12
0
3
Bit 11
0
2
Bit 10
0
1
Bit 9
0
0
Bit 8
0
Figure 8-17. Debug Comparator Address Mid Register (DBGXAM)
Read: Anytime. See Table 8-23 for visible register encoding.
Write: If DBG not armed. See Table 8-23 for visible register encoding.
Table 8-25. DBGXAM Field Descriptions
Field
7–0
Bit[15:8]
Description
Comparator Address Mid Compare Bits — The Comparator address mid compare bits control whether the
selected comparator compares the address bus bits [15:8] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
MC9S12G Family Reference Manual, Rev.1.10
292
Freescale Semiconductor