S9S12G128F0CLF Datasheet, PDF (337/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

S12 Clock, Reset and Power Management Unit (S12CPMU)
Table 10-3. CPMUFLG Field Descriptions (continued)
Field
1
OSCIF
0
UPOSC
Description
Oscillator Interrupt Flag — OSCIF is set to 1 when UPOSC status bit changes. This flag can only be cleared
by writing a 1. Writing a 0 has no effect.If enabled (OSCIE=1), OSCIF causes an interrupt request.
0 No change in UPOSC bit.
1 UPOSC bit has changed.
Oscillator Status Bit — UPOSC reflects the status of the oscillator. Writes have no effect. While UPOSC=0 the
OSCCLK going to the MSCAN module is off. Entering Full Stop Mode UPOSC is cleared.
0 The oscillator is off or oscillation is not qualified by the PLL.
1 The oscillator is qualified by the PLL.
10.3.2.5 S12CPMU Interrupt Enable Register (CPMUINT)
This register enables S12CPMU interrupt requests.
0x0038
7
6
R
0
RTIE
W
5
4
3
0
0
LOCKIE
2
1
0
0
0
OSCIE
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-8. S12CPMU Interrupt Enable Register (CPMUINT)
Read: Anytime
Write: Anytime
Table 10-4. CRGINT Field Descriptions
Field
7
RTIE
4
LOCKIE
1
OSCIE
Description
Real Time Interrupt Enable Bit
0 Interrupt requests from RTI are disabled.
1 Interrupt will be requested whenever RTIF is set.
PLL Lock Interrupt Enable Bit
0 PLL LOCK interrupt requests are disabled.
1 Interrupt will be requested whenever LOCKIF is set.
Oscillator Corrupt Interrupt Enable Bit
0 Oscillator Corrupt interrupt requests are disabled.
1 Interrupt will be requested whenever OSCIF is set.
10.3.2.6 S12CPMU Clock Select Register (CPMUCLKS)
This register controls S12CPMU clock selection.
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
337