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S9S12G128F0CLF Datasheet, PDF (275/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual | |||
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Chapter 8
S12S Debug Module (S12SDBG)
Revision History
Revision Number
Date
02.00
31.JUL..2007
02.01
02.02
09.AUG..2007
10.AUG..2007
02.03
29.AUG..2007
02.04
02.05
17.OCT.2007
19.OCT.2007
02.06
22.NOV.2007
02.07
13.DEC.2007
Author
Summary of Changes
State sequencer encoding enhanced
Simultaneous TRIG and ARM setting updated
Pure PC replaced with Compressed Pure PC Mode 8.4.5.2.4
Enhanced compressed Pure PC mode description
Added CompA size & databus byte compare enhancement
DBGSCR1 encoding 1101 added.
CompA functional description improved
Swapped NDB and SZ in DBGACTL to match DBGBCTL
Reverted to ï¬nal state transition priority
Table 8-33 DB byte access conï¬guration corrected
Table 8-39 Correction
Section 8.4.5.6, âTrace Buffer Reset State Added NOTE
Section 8.5, âApplication Information Added application
information
8.1 Introduction
The S12SDBG module provides an on-chip trace buffer with ï¬exible triggering capability to allow
non-intrusive debug of application software. The S12SDBG module is optimized for S12SCPU
debugging.
Typically the S12SDBG module is used in conjunction with the S12SBDM module, whereby the user
conï¬gures the S12SDBG module for a debugging session over the BDM interface. Once conï¬gured the
S12SDBG module is armed and the device leaves BDM returning control to the user program, which is
then monitored by the S12SDBG module. Alternatively the S12SDBG module can be conï¬gured over a
serial interface using SWI routines.
8.1.1 Glossary Of Terms
COF: Change Of Flow. Change in the program ï¬ow due to a conditional branch, indexed jump or interrupt.
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
275
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