S9S12G128F0CLF Datasheet, PDF (353/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.3.2.18 S12CPMU IRC1M Trim Registers (CPMUIRCTRIMH / CPMUIRCTRIML)
0x02F8
15
14
13
12
11
10
R
0
TCTRIM[4:0]
W
9
8
IRCTRIM[9:8]
Reset
F
F
F
F
0
0
F
F
After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to
provide trimmed Internal Reference Frequency f_{IRC1M_TRIM}.
Figure 10-23. S12CPMU IRC1M Trim High Register (CPMUIRCTRIMH)
0x02F9
7
6
5
4
3
2
1
0
R
IRCTRIM[7:0]
W
Reset
F
F
F
F
F
F
F
F
After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to
provide trimmed Internal Reference Frequency f_{IRC1M_TRIM}.
Figure 10-24. S12CPMU IRC1M Trim Low Register (CPMUIRCTRIML)
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register). Else write has no effect
NOTE
Writes to these registers while PLLSEL=1 clears the LOCK and UPOSC
status bits.
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
353