S9S12G128F0CLF Datasheet, PDF (448/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Analog-to-Digital Converter (ADC12B16CV2)
Table 14-3. ATDCTL1 Field Descriptions
Field
Description
7
ETRIGSEL
External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
channels or one of the ETRIG3-0 inputs. See device specification for availability and connectivity of ETRIG3-0
inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has
no effect, this means that one of the AD channels (selected by ETRIGCH3-0) is configured as the source for
external trigger. The coding is summarized in Table 14-5.
6–5
A/D Resolution Select — These bits select the resolution of A/D conversion results. See Table 14-4 for
SRES[1:0] coding.
4
SMP_DIS
Discharge Before Sampling Bit
0 No discharge before sampling.
1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to
the sampling time. This can help to detect an open circuit instead of measuring the previous sampled
channel.
3–0
External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs
ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Table 14-5.
Table 14-4. A/D Resolution Coding
SRES1
SRES0
A/D Resolution
0
0
8-bit data
0
1
10-bit data
1
0
12-bit data
1
1
Reserved
Table 14-5. External Trigger Channel Select Coding
ETRIGSEL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
ETRIGCH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
ETRIGCH2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
ETRIGCH1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
ETRIGCH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
External trigger source is
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
ETRIG0¹
ETRIG1¹
MC9S12G Family Reference Manual, Rev.1.10
448
Freescale Semiconductor