S9S12G128F0CLF Datasheet, PDF (346/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

S12 Clock, Reset and Power Management Unit (S12CPMU)
Table 10-14. COP Watchdog Rates if COPOSCSEL1=1
CR2
0
0
0
0
1
1
1
1
CR1
0
0
1
1
0
0
1
1
CR0
0
1
0
1
0
1
0
1
COPCLK
Cycles to Time-out
(COPCLK is ACLK -
internal RC-Oscillator clock)
COP disabled
2⁷
2⁹
2 ¹¹
2 ¹³
2 ¹⁵
2 ¹⁶
2 ¹⁷
10.3.2.10 Reserved Register CPMUTEST0
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in Special
Mode can alter the S12CPMU’s functionality.
0x003D
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-13. Reserved Register (CPMUTEST0)
Read: Anytime
Write: Only in Special Mode
10.3.2.11 Reserved Register CPMUTEST1
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in Special
Mode can alter the S12CPMU’s functionality.
MC9S12G Family Reference Manual, Rev.1.10
346
Freescale Semiconductor