S9S12G128F0CLF Datasheet, PDF (361/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

S12 Clock, Reset and Power Management Unit (S12CPMU)
Figure 10-30. Startup of clock system after Reset
System
Reset
PLLCLK
768 cycles
f_VCORST
)(
LOCK
f_PLL increasing
t_lock
f_PLL=16MHz
f_PLL=32 MHz
SYNDIV $18 (default target f_VCO=50MHz)
POSTDIV $03 (default target f_PLL=f_VCO/4 = 12.5MHz)
CPU
reset state
vector fetch, program execution
$01
example change
of POSTDIV
10.4.3 Stop Mode using PLLCLK as Bus Clock
An example of what happens going into Stop Mode and exiting Stop Mode after an interrupt is shown in
Figure 10-31. Disable PLL Lock interrupt (LOCKIE=0) before going into Stop Mode.
Figure 10-31. Stop Mode using PLLCLK as Bus Clock
wakeup
CPU ^execution
PLLCLK
LOCK
STOP instruction
t_{STP_REC}
interrupt continue execution
t_lock
10.4.4 Full Stop Mode using Oscillator Clock as Bus Clock
An example of what happens going into Full Stop Mode and exiting Full Stop Mode after an interrupt is
shown in Figure 10-32.
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
361