S9S12G128F0CLF Datasheet, PDF (401/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Analog-to-Digital Converter (ADC10B12CV2)
12.3.2.3 ATD Control Register 2 (ATDCTL2)
Writes to this register will abort current conversion sequence.
Module Base + 0x0002
7
R
0
W
Reset
0
Read: Anytime
Write: Anytime
6
AFFC
5
Reserved
4
ETRIGLE
3
ETRIGP
2
ETRIGE
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-5. ATD Control Register 2 (ATDCTL2)
Table 12-6. ATDCTL2 Field Descriptions
1
ASCIE
0
0
ACMPIE
0
Field
Description
6
AFFC
5
Reserved
4
ETRIGLE
3
ETRIGP
2
ETRIGE
1
ASCIE
0
ACMPIE
ATD Fast Flag Clear All
0 ATD flag clearing done by write 1 to respective CCF[n] flag.
1 Changes all ATD conversion complete flags to a fast clear sequence.
For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] flag
to clear automatically.
For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] flag
to clear automatically.
Do not alter this bit from its reset value.It is for Manufacturer use only and can change the ATD behavior.
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
Table 12-7 for details.
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 12-7 for details.
External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of the
ETRIG3-0 inputs as described in Table 12-5. If the external trigger source is one of the AD channels, the digital
input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with
external events.
0 Disable external trigger
1 Enable external trigger
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set.
ATD Compare Interrupt Enable — If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE
register) this bit enables the compare interrupt. If the CCF[n] flag is set (showing a successful compare for
conversion n), the compare interrupt is triggered.
0 ATD Compare interrupt requests are disabled.
1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), an ATD Compare
Interrupt will be requested whenever any of the respective CCF flags is set.
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
401