S9S12G128F0CLF Datasheet, PDF (644/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Timer Module (TIM16B8CV3)
Read: Anytime
Write: Anytime for output compare function.Writes to these registers have no meaning or effect during
input capture. All timer input capture/output compare registers are reset to 0x0000.
NOTE
Read/Write access in byte mode for high byte should takes place before low
byte otherwise it will give a different result.
20.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL)
7
R
0
W
6
5
4
3
2
1
0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
Reset
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 20-24. 16-Bit Pulse Accumulator Control Register (PACTL)
1 _{This register is available only when channel 7 exists and is reserved if that channel does not exist. Writes to a reserved register}
have no functional effect. Reads from a reserved register return zeroes.
Read: Any time
Write: Any time
When PAEN is set, the Pulse Accumulator counter is enabled.The Pulse Accumulator counter shares the
input pin with IOC7.
Table 20-18. PACTL Field Descriptions
Field
6
PAEN
5
PAMOD
4
PEDGE
Description
Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator system disabled.
1 Pulse Accumulator system enabled.
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See
Table 20-19.
0 Event counter mode.
1 Gated time accumulation mode.
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1).
For PAMOD bit = 0 (event counter mode). See Table 20-19.
0 Falling edges on IOC7 pin cause the count to be increased.
1 Rising edges on IOC7 pin cause the count to be increased.
For PAMOD bit = 1 (gated time accumulation mode).
0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling
edge on IOC7 sets the PAIF flag.
1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge
on IOC7 sets the PAIF flag.
MC9S12G Family Reference Manual, Rev.1.10
644
Freescale Semiconductor