S9S12G128F0CLF Datasheet, PDF (222/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

5V Analog Comparator (ACMPV1)
3.7 Functional Description
The ACMP compares two analog input voltages applied to ACMPM and ACMPP. The comparator output
is high when the voltage at the non-inverting input is greater than the voltage at the inverting input, and is
low when the non-inverting input voltage is lower than the inverting input voltage.
The ACMP is enabled with register bit ACMPC[ACE]. When ACMPC[ACE] is set, the input pins are
connected to low-pass filters. The comparator output is disconnected from the subsequent logic, which is
held at its state for 63 bus clock cycles after setting ACMPC[ACE] to “1” to mask potential glitches. This
initialization delay must be accounted for before the first comparison result can be expected.
The initial hold state after reset is zero, thus if input voltages are set to result in “true” result
(V_ACMPP > V_ACMPM) before the initialization delay has passed, a flag will be set immediately after this.
Similarly the flag will also be set when disabling the ACMP, then re-enabling it with the inputs changing
to produce an opposite result to the hold state before the end of the initialization delay.
By setting the ACMPC[ACICE] bit the gated comparator output can be connected to the synchronized
timer input capture channel 5 (see Figure 3-1). This feature can be used to generate time stamps and timer
interrupts on ACMP events.
The comparator output signal synchronized to the bus clock is used to read the comparator output status
(ACMPS[ACO]) and to set the interrupt flag (ACMPS[ACIF]).
The condition causing the interrupt flag (ACMPS[ACIF]) to assert is selected with register bits
ACMPC[ACMOD1:ACMOD0]. This includes any edge configuration, that is rising, or falling, or rising
and falling (toggle) edges of the comparator output. Also flag setting can be disabled.
An interrupt will be generated if the interrupt enable bit (ACMPC[ACIE]) and the interrupt flag
(ACMPS[ACIF]) are both set. ACMPS[ACIF] is cleared by writing a 1.
The raw comparator output signal ACMPO can be driven out on an external pin by setting the
ACMPC[ACOPE] bit.
3.8 Initialization/Application Information
3.8.1 VDDX Over-Voltage Monitor
The ACMP can be configured to compare the internally downscaled voltage present on the VDDX supply
against a constant internal reference for over-voltage detection. In this case the ACMPM and ACMPP
input signals are disconnected from the comparator.
The standard output features of the ACMP like interrupt flag and external digital output can be used to
display the result. Alternatively pin ACMPO1 can be used as digital output to control an external
component. An over-voltage event is triggered if the supply voltage on VDDX exceeds V_VDDXassert.
In order to setup the module for over-voltage monitoring also refer to PIM section “Pin Routing Register
2 (PRR2)”.
MC9S12G Family Reference Manual, Rev.1.10
222
Freescale Semiconductor