S9S12G128F0CLF Datasheet, PDF (636/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Timer Module (TIM16B8CV3)
20.3.2.5 Timer Count Register (TCNT)
R
W
Reset
15
TCNT15
0
14
TCNT14
13
TCNT13
12
TCNT12
11
TCNT11
10
TCNT10
0
0
0
0
0
Figure 20-10. Timer Count Register High (TCNTH)
9
TCNT9
0
9
TCNT8
0
R
W
Reset
7
TCNT7
0
6
TCNT6
5
TCNT5
4
TCNT4
3
TCNT3
2
TCNT2
0
0
0
0
0
Figure 20-11. Timer Count Register Low (TCNTL)
1
TCNT1
0
0
TCNT0
0
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give a different result than accessing them as a word.
Read: Anytime
Write: Has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1).
The period of the first count after a write to the TCNT registers may be a different size because the write
is not synchronized with the prescaler clock.
20.3.2.6 Timer System Control Register 1 (TSCR1)
7
6
5
4
3
2
1
0
R
0
0
0
TEN
TSWAI
TSFRZ
TFFCA
PRNT
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 20-12. Timer System Control Register 1 (TSCR1)
Read: Anytime
Write: Anytime
MC9S12G Family Reference Manual, Rev.1.10
636
Freescale Semiconductor