S9S12G128F0CLF Datasheet, PDF (119/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Port Integration Module (S12GPIMV1)
• Key-wakeup feature: External pin interrupt with glitch filtering, which can also be used for wakeup
from stop mode.
2.1.4 Block Diagram
Figure 2-1. Block Diagram
n
1
0
Peripheral
Module
PIM
Ports
Pin Enable, Data
Data
Control
Pin Enable, Data
PIM
Routing _Data
Control
Package Code
Pin Routing (20 TSSOP only)
Pin #0
Pin #n
2.2 PIM Routing - External Signal Description
This section lists and describes the signals that do connect off-chip.
Table 2-3 shows the availability of I/O port pins for each group in the largest offered package option.
Table 2-3. Port Pin Availability (in largest package) per Device
Device Group
Port
G1
G2
G3
(100 pin)
(64 pin)
(48 pin)
A
7-0
-
-
B
7-0
-
-
C
7-0
-
-
D
7-0
-
-
E
1-0
1-0
1-0
T
7-0
7-0
5-0
S
7-0
7-0
7-0
M
3-0
3-0
1-0
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
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