S9S12G128F0CLF Datasheet, PDF (646/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Timer Module (TIM16B8CV3)
20.3.2.16 Pulse Accumulator Flag Register (PAFLG)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
PAOVF
PAIF
W
Reset
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 20-25. Pulse Accumulator Flag Register (PAFLG)
1 _{This register is available only when channel 7 exists and is reserved if that channel does not exist. Writes to a reserved register}
have no functional effect. Reads from a reserved register return zeroes.
Read: Anytime
Write: Anytime
When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags
in the PAFLG register. Timer module or Pulse Accumulator must stay enabled (TEN=1 or PAEN=1) while
clearing these bits.
Table 20-21. PAFLG Field Descriptions
Field
1
PAOVF
0
PAIF
Description
Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000.
Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of
PACTL register is set to one.
Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the IOC7 input pin triggers PAIF.
Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of
PACTL register is set to one. Any access to the PACNT register will clear all the flags in this register when TFFCA
bit in register TSCR(0x0006) is set.
20.3.2.17 Pulse Accumulators Count Registers (PACNT)
15
R
PACNT15
W
14
PACNT14
13
PACNT13
12
PACNT12
11
PACNT11
10
PACNT10
9
PACNT9
Reset
0
0
0
0
0
0
0
Figure 20-26. Pulse Accumulator Count Register High (PACNTH)
0
PACNT8
0
MC9S12G Family Reference Manual, Rev.1.10
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Freescale Semiconductor