S9S12G128F0CLF Datasheet, PDF (363/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

S12 Clock, Reset and Power Management Unit (S12CPMU)
OSCE
EXTAL
UPOSC
Figure 10-33. Enabling the External Oscillator
enable external Oscillator by writing OSCE bit to one.
crystal/resonator starts oscillating
UPOSC flag is set upon successful start of oscillation
OSCCLK
PLLSEL
Core
Clock
select OSCCLK as Core/Bus Clock by writing PLLSEL to zero
based on PLLCLK
based on OSCCLK
10.4.6 System Clock Configurations
10.4.6.1 PLL Engaged Internal Mode (PEI)
This mode is the default mode after System Reset or Power-On Reset.
The Bus clock is based on the PLLCLK, the reference clock for the PLL is internally generated (IRC1M).
The PLL is configured to 50 MHz VCOCLK with POSTDIV set to 0x03. If locked (LOCK=1) this results
in a PLLCLK of 12.5 MHz and a Bus clock of 6.25 MHz. The PLL can be re-configured to other bus
frequencies.
The clock sources for COP and RTI can be based on the internal reference clock generator (IRC1M) or the
RC-Oscillator (ACLK).
10.4.6.2 PLL Engaged External Mode (PEE)
In this mode, the Bus clock is based on the PLLCLK as well (like PEI). The reference clock for the PLL
is based on the external oscillator.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the
external oscillator clock or the RC-Oscillator (ACLK).
This mode can be entered from default mode PEI by performing the following steps:
1. Configure the PLL for desired bus frequency.
2. Enable the external oscillator (OSCE bit).
3. Wait for oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1).
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
363