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S9S12G128F0CLF Datasheet, PDF (457/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual | |||
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Analog-to-Digital Converter (ADC12B16CV2)
Table 14-16. ATDSTAT0 Field Descriptions
Field
7
SCF
5
ETORF
4
FIFOR
3â0
CC[3:0]
Description
Sequence Complete Flag â This ï¬ag is set upon completion of a conversion sequence. If conversion
sequences are continuously performed (SCAN=1), the ï¬ag is set after each one is completed. This ï¬ag is cleared
when one of the following occurs:
A) Write â1â to SCF
B) Write to ATDCTL5 (a new conversion sequence is started)
C) If AFFC=1 and a result register is read
0 Conversion sequence not completed
1 Conversion sequence has completed
External Trigger Overrun Flag â While in edge sensitive mode (ETRIGLE=0), if additional active edges are
detected while a conversion sequence is in process the overrun ï¬ag is set. This ï¬ag is cleared when one of the
following occurs:
A) Write â1â to ETORF
B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
0 No External trigger overrun error has occurred
1 External trigger overrun error has occurred
Result Register Overrun Flag â This bit indicates that a result register has been written to before its associated
conversion complete ï¬ag (CCF) has been cleared. This ï¬ag is most useful when using the FIFO mode because
the ï¬ag potentially indicates that result registers are out of sync with the input channels. However, it is also
practical for non-FIFO modes, and indicates that a result register has been overwritten before it has been read
(i.e. the old data has been lost). This ï¬ag is cleared when one of the following occurs:
A) Write â1â to FIFOR
B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
0 No overrun has occurred
1 Overrun condition exists (result register has been written while associated CCFx ï¬ag was still set)
Conversion Counter â These 4 read-only bits are the binary value of the conversion counter. The conversion
counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1,
CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO
mode (FIFO=0) the conversion counter is initialized to zero at the beginning and end of the conversion sequence.
If in FIFO mode (FIFO=1) the register counter is not initialized. The conversion counter wraps around when its
maximum value is reached.
Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1.
14.3.2.8 ATD Compare Enable Register (ATDCMPE)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
457
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