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S9S12G128F0CLF Datasheet, PDF (499/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual | |||
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Freescaleâs Scalable Controller Area Network (S12MSCANV3)
16.3.2.17 MSCAN Identiï¬er Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identiï¬er acceptance and identiï¬er mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0âIDR3 registers (see Section 16.3.3.1,
âIdentiï¬er Registers (IDR0âIDR3)â) of incoming messages in a bit by bit manner (see Section 16.4.3,
âIdentiï¬er Acceptance Filterâ).
For extended identiï¬ers, all four acceptance and mask registers are applied. For standard identiï¬ers, only
the ï¬rst two (CANIDAR0/1, CANIDMR0/1) are applied.
Module Base + 0x0010 to Module Base + 0x0013
Access: User read/write1
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
Figure 16-20. MSCAN Identiï¬er Acceptance Registers (First Bank) â CANIDAR0âCANIDAR3
1 Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 16-22. CANIDAR0âCANIDAR3 Register Field Descriptions
Field
7-0
AC[7:0]
Description
Acceptance Code Bits â AC[7:0] comprise a user-deï¬ned sequence of bits with which the corresponding bits
of the related identiï¬er register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identiï¬er mask register.
Module Base + 0x0018 to Module Base + 0x001B
Access: User read/write1
7
R
AC7
W
Reset
0
6
AC6
0
5
AC5
0
4
AC4
0
3
AC3
0
2
AC2
0
1
AC1
0
0
AC0
0
Figure 16-21. MSCAN Identiï¬er Acceptance Registers (Second Bank) â CANIDAR4âCANIDAR7
1 Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
499
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