S9S12G128F0CLF Datasheet, PDF (647/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Timer Module (TIM16B8CV3)
7
R
PACNT7
W
6
PACNT6
5
PACNT5
4
PACNT4
3
PACNT3
2
PACNT2
1
PACNT1
0
PACNT0
Reset
0
0
0
0
0
0
0
0
Figure 20-27. Pulse Accumulator Count Register Low (PACNTL)
1 _{This register is available only when channel 7 exists and is reserved if that channel does not exist. Writes to a reserved register}
have no functional effect. Reads from a reserved register return zeroes.
Read: Anytime
Write: Anytime
These registers contain the number of active input edges on its input pin since the last reset.
When PACNT overflows from 0xFFFF to 0x0000, the Interrupt flag PAOVF in PAFLG (0x0021) is set.
Full count register access should take place in one clock cycle. A separate read/write for high byte and low
byte will give a different result than accessing them as a word.
NOTE
Reading the pulse accumulator counter registers immediately after an active
edge on the pulse accumulator input pin may miss the last count because the
input has to be synchronized with the bus clock first.
20.3.2.18 Output Compare Pin Disconnect Register(OCPD)
R
W
Reset
7
OCPD7
0
6
OCPD6
5
OCPD5
4
OCPD4
3
OCPD3
2
OCPD2
1
OCPD1
0
0
0
0
0
0
Figure 20-28. Output Compare Pin Disconnect Register (OCPD)
0
OCPD0
0
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 20-22. OCPD Field Description
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
unavailable bits return a zero.
Field
Description
OCPD[7:0}
Output Compare Pin Disconnect Bits
0 Enables the timer channel port. Output Compare action will occur on the channel pin. These bits do not affect
the input capture or pulse accumulator functions
1 Disables the timer channel port. Output Compare action will not occur on the channel pin, but the output
compare flag still become set.
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
647