S9S12G128F0CLF Datasheet, PDF (450/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Analog-to-Digital Converter (ADC12B16CV2)
Table 14-6. ATDCTL2 Field Descriptions (continued)
Field
1
ASCIE
0
ACMPIE
Description
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set.
ATD Compare Interrupt Enable — If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE
register) this bit enables the compare interrupt. If the CCF[n] flag is set (showing a successful compare for
conversion n), the compare interrupt is triggered.
0 ATD Compare interrupt requests are disabled.
1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), an ATD Compare
Interrupt will be requested whenever any of the respective CCF flags is set.
Table 14-7. External Trigger Configurations
ETRIGLE
0
0
1
1
ETRIGP
0
1
0
1
External Trigger Sensitivity
Falling edge
Rising edge
Low level
High level
14.3.2.4 ATD Control Register 3 (ATDCTL3)
Writes to this register will abort current conversion sequence.
Module Base + 0x0003
R
W
Reset
7
DJM
0
Read: Anytime
Write: Anytime
6
S8C
5
S4C
4
S2C
3
S1C
2
FIFO
0
1
0
0
0
= Unimplemented or Reserved
Figure 14-6. ATD Control Register 3 (ATDCTL3)
1
FRZ1
0
0
FRZ0
0
MC9S12G Family Reference Manual, Rev.1.10
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Freescale Semiconductor