S9S12G128F0CLF Datasheet, PDF (1080/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Electrical Characteristics
Table A-10. Peripheral Configurations for Run & Wait Current Measurement
Peripheral
Configuration
MSCAN
Configured to loop-back mode using a bit rate of 1Mbit/s
SPI
Configured to master mode, continuously transmit data
(0x55 or 0xAA) at 1Mbit/s
SCI
Configured into loop mode, continuously transmit data
(0x55) at speed of 57600 baud
PWM
ADC
Configured to toggle its pins at the rate of 40kHz
The peripheral is configured to operate at its maximum
specified frequency and to continuously convert voltages on
all input channels in sequence.
DBG
The module is enabled and the comparators are configured
to trigger in outside range.The range covers all the code
executed by the core.
TIM
The peripheral shall be configured to output compare mode,
pulse accumulator and modulus counter enabled.
COP & RTI
Both modules are enabled.
ACMP¹
The module is enabled with analog output on. The ACMPP
and ACMPM are toggling with 0-1 and 1-0.
DAC²
DAC0 and DAC1 is buffered at full voltage range
(DACxCTL = $87).
RVA³
The module is enabled and ADC is running at 6.25MHz with
maximum bus freq
1 _{Onlly available on S12GN16, S12GN32, S12GN48, S12G48, and S12G64}
2 _{Only available on S12G192, S12GA192, S12G340, and S12GA240}
3 _{Only available on S12GA192 and S12GA240}
1080
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor