S9S12G128F0CLF Datasheet, PDF (589/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Serial Communication Interface (S12SCIV5)
Perceived Start Bit
Actual Start Bit
LSB
RXD
Samples 1 1 1 0
0
1
0000
RT Clock
RT Clock Count
Reset RT Clock
Figure 18-24. Start Bit Search Example 3
Figure 18-25 shows the effect of noise early in the start bit time. Although this noise does not affect proper
synchronization with the start bit time, it does set the noise flag.
Perceived and Actual Start Bit
LSB
RXD
Samples 1 1 1 1 1 1 1 1 1 0
1
0
RT Clock
RT Clock Count
Reset RT Clock
Figure 18-25. Start Bit Search Example 4
Figure 18-26 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample
after the reset is low but is not preceded by three high samples that would qualify as a falling edge.
Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may
set the framing error flag.
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
589