S9S12G128F0CLF Datasheet, PDF (283/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

S12S Debug Module (S12SDBG)
8.3.2.4 Debug Control Register2 (DBGC2)
Address: 0x0023
7
R
0
W
Reset
0
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-6. Debug Control Register2 (DBGC2)
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
Table 8-8. DBGC2 Field Descriptions
1
0
ABCM
0
0
Field
Description
1–0
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
ABCM[1:0] described in Table 8-9.
Table 8-9. ABCM Encoding
ABCM
Description
00
Match0 mapped to comparator A match: Match1 mapped to comparator B match.
01
Match 0 mapped to comparator A/B inside range: Match1 disabled.
10
Match 0 mapped to comparator A/B outside range: Match1 disabled.
11
Reserved¹
1 _{Currently defaults to Comparator A, Comparator B disabled}
8.3.2.5 Debug Trace Buffer Register (DBGTBH:DBGTBL)
Address: 0x0024, 0x0025
15
14
13
12
11
10
9
R
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
W
POR X X X X X X X
Other
Resets
—
—
—
—
—
—
—
8
Bit 8
X
—
7
Bit 7
X
—
6
Bit 6
X
—
5
Bit 5
X
—
4
Bit 4
X
—
3
Bit 3
X
—
2
Bit 2
X
—
1
Bit 1
X
—
0
Bit 0
X
—
Figure 8-7. Debug Trace Buffer Register (DBGTB)
Read: Only when unlocked AND unsecured AND not armed AND TSOURCE set.
Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer
contents.
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
283