S9S12G128F0CLF Datasheet, PDF (447/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Analog-to-Digital Converter (ADC12B16CV2)
Table 14-2. Multi-Channel Wrap Around Coding
WRAP3 WRAP2 WRAP1 WRAP0
Multiple Channel Conversions (MULT = 1)
Wraparound to AN0 after Converting
0
0
0
0
Reserved¹
0
0
0
1
AN1
0
0
1
0
AN2
0
0
1
1
AN3
0
1
0
0
AN4
0
1
0
1
AN5
0
1
1
0
AN6
0
1
1
1
AN7
1
0
0
0
AN8
1
0
0
1
AN9
1
0
1
0
AN10
1
0
1
1
AN11
1
1
0
0
AN12
1
1
0
1
AN13
1
1
1
0
AN14
1
1
1
1
AN15
1_{If only AN0 should be converted use MULT=0.}
14.3.2.2 ATD Control Register 1 (ATDCTL1)
Writes to this register will abort current conversion sequence.
Module Base + 0x0001
7
R
ETRIGSEL
W
Reset
0
6
SRES1
5
SRES0
4
3
2
1
0
SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
0
1
0
1
1
1
1
Figure 14-4. ATD Control Register 1 (ATDCTL1)
Read: Anytime
Write: Anytime
MC9S12G Family Reference Manual, Rev.1.10
Freescale Semiconductor
447