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S9S12G128F0CLF Datasheet, PDF (122/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual | |||
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Port Integration Module (S12GPIMV1)
Table 2-4. Signals and Priorities
Port Pin
Signal
Signals per Device and Package
(signal priority on pin from top to bottom)
Legend
â Signal available on pin
â Routing option on pin
â Routing reset location
Not available on pin
I/O
Description
100
64
48
32
20
C
PC7
DACU1 â
O DAC1 output unbuffered
[PC7]
â â â
I/O GPIO
PC6
AMPP1 â
I DAC1 non-inv. input (+)
[PC6]
â â â
I/O GPIO
PC5
AMPM1 â
I DAC1 inverting input (-)
[PC5]
â â â
I/O GPIO
PC4-PC2 AN15-AN13 â â
I ADC analog
[PC4:PC2] â â â
I/O GPIO
PC1-PC0 AN11-AN10 â â
I ADC analog
[PC1:PC0] â â â
I/O GPIO
D PD7-PD0 [PD7:PD0] â â â
I/O GPIO
E
PE1
XTAL
â â â â â â â â â â â â â â â â â â â â â - CPMU OSC signal
TXD0
â â I/O SCI transmit
IOC3
â â I/O Timer channel
PWM1
â â O PWM channel
ETRIG1
â â I ADC external trigger
[PE1]
â â â â â â â â â â â â â â â â â â â â â I/O GPIO
PE0
EXTAL â â â â â â â â â â â â â â â â â â â â â - CPMU OSC signal
RXD0
â â I SCI receive
IOC2
â â I/O Timer channel
PWM0
â â O PWM channel
ETRIG0
â â I ADC external trigger
[PE0]
â â â â â â â â â â â â â â â â â â â â â I/O GPIO
MC9S12G Family Reference Manual, Rev.1.10
122
Freescale Semiconductor
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