S9S12G128F0CLF Datasheet, PDF (400/1158 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual

Analog-to-Digital Converter (ADC10B12CV2)
Table 12-3. ATDCTL1 Field Descriptions (continued)
Field
Description
4
SMP_DIS
Discharge Before Sampling Bit
0 No discharge before sampling.
1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to
the sampling time. This can help to detect an open circuit instead of measuring the previous sampled
channel.
3–0
External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs
ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Table 12-5.
Table 12-4. A/D Resolution Coding
SRES1
SRES0
A/D Resolution
0
0
8-bit data
0
1
10-bit data
1
0
1
1
Reserved
Table 12-5. External Trigger Channel Select Coding
ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is
0
0
0
0
0
AN0
0
0
0
0
1
AN1
0
0
0
1
0
AN2
0
0
0
1
1
AN3
0
0
1
0
0
AN4
0
0
1
0
1
AN5
0
0
1
1
0
AN6
0
0
1
1
1
AN7
0
1
0
0
0
AN8
0
1
0
0
1
AN9
0
1
0
1
0
AN10
0
1
0
1
1
AN11
0
1
1
0
0
AN11
0
1
1
0
1
AN11
0
1
1
1
0
AN11
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
AN11
ETRIG0¹
ETRIG1¹
ETRIG2¹
ETRIG3¹
1
0
1
X
X
Reserved
1
1
X
X
X
Reserved
1 _{Only if ETRIG3-0 input option is available (see device specification), else ETRISEL is ignored, that means}
external trigger source is still on one of the AD channels selected by ETRIGCH3-0
MC9S12G Family Reference Manual, Rev.1.10
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