K4Y50164UC Datasheet, PDF (75/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
List of Figures
1. XDR DRAM Device Write and Read Transactions............. 5
2. 512Mb (8x4Mx16)XDR DRAM Block Diagram .................. 12
3. Request Packet Formats ................................................... 14
4. ACT-, RD-, WR-, PRE-to-ACT Packet Interactions........... 19
5. ACT-, RD-, WR-, PRE-to-RD Packet Interactions............. 20
6. ACT-, RD-, WR-, PRE-to-WR Packet Interactions ............ 21
7. ACT-, RD-, WR-, PRE-to-PRE Packet Interactions........... 22
8. Request Scheduling Examples......................................... 23
9. Write Transactions............................................................. 26
10. Read Transactions ........................................................... 28
11. Interleaved Transactions ................................................. 30
12. Write/Read Interaction ..................................................... 31
13. Propagation Delay............................................................ 33
14. Serial Write Transaction .................................................. 35
15. Serial Read Transaction-Selected DRAM ...................... 35
16. Serial Read Transaction-Non-Selected DRAM .............. 35
17. Serial Identification(SID) Register .................................. 36
18. Configuration (CFG) Register ......................................... 37
19. Power Management(PM) Register .................................. 37
20. Write Data Serial Load(WDSL) Control Register ........... 37
21. RQ Scan High(RQH) Register ......................................... 37
22. RQ Scan Low(RQL) Register........................................... 38
23. Refresh Bank (REFB) Control Register.......................... 38
24. Refresh High (REFH) Row Register................................ 38
25. Refresh Middle(REFM) Row Register............................. 38
26. Refresh Low (REFL) Row Register................................. 39
27. IO Configuration (IOCFG) Register................................. 39
28. Current Calibration 0 (CC0) Register ............................. 39
29. Current Calibration 1 (CC1) Register ............................. 39
30. Impedance Calibration 0 (ZC0) Register ........................ 39
31. Impedance Calibration 1 (ZC1) Register ........................ 39
32. Current Fuse Setting 0 (FZC0) Register......................... 40
33. Current Fuse Setting 1 (FZC1) Register......................... 40
34. Read Only Memory 0 (ROM0) Register ......................... .40
35. Read Only Memory 1 (ROM1) Register .......................... 40
36. Test Register .................................................................... 40
37. DLL Register..................................................................... 40
38. PLL0 Register ................................................................... 41
39. PLL1 Register ................................................................... 41
40. IFT Register ...................................................................... 41
41. DA Register....................................................................... 41
42. Delay(DLY) Control Register........................................... 41
43. Partner-Definable (PART0-PARTF) Registers ............... 41
44. Refresh Transactions ...................................................... 43
45. Calibration Transactions ................................................. 44
46. Power State Management................................................ 46
47. Serial Interface Systems Topology ................................ 47
48. Initialization Timing for XDR DRAM [k] Device ............. 47
49. Sub-Row Example............................................................ 50
50. Byte Mask Logic............................................................... 51
51. Wirte-Masked (WRM) Transaction Example ...................... 52
52. Wirte/Read Interaction-No ERAW Feature ......................... 53
53. Write/Read Interaction-ERAW Feature............................... 53
54. XDR DRAM Block Diagram with Bank Sets ....................... 54
55. Simultaneous Activation-tRR-D Cased .............................. 55
56. Simultaneous Precharge-tPP-D Cases .............................. 56
57. Clocking Waveforms............................................................ 62
58. RSL RQ Receive Waveforms............................................... 63
59. DRSL DQ Receive Waveforms ........................................... .65
60. RSL DQ Transimit Waveforms ............................................ 67
61. Serial Interface Receive Waveforms .................................. 68
62. Serial Interface Transmit Waveforms................................. 69
63. Equivalent Circuits for Package Parasitic ......................... 71
75 of 76
Rev. 1.1 August 2006