K4Y50164UC Datasheet, PDF (38/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
Figure 22 : RQ Scan Low (RQL) Register
76543210
RQL[7:0]
RQ Scan Low Register
SADR[7:0]: 00000111₂
Read/write register
RQL[7:0] resets to 00000000₂
RQL[7:0] - Latched value of RQ[7:0] in RQ wire test mode.
76
MBR[1:0]
Figure 23 : Refresh Bank (REFB) Control Register
543
reserved
210
BANK[2:0]
Refresh Bank Control Register
Read/write register
SADR[7:0]: 00001000₂
REFB[7:0] resets to 00000000₂
BANK[2:0] - Refresh bank field.
This field returns the bank address for the next self-refresh
operation when in Powerdown power state.
MBR[1:0] - Multi-bank and multi-row refresh control field.
00₂ - Single-bank refresh.
01₂ - Reserved
10₂ - Reserved
11₂ - Reserved
Figure 24 : Refresh High (REFH) Row Register
76543210
reserved
R[18:16]
Refresh High Row Register
Read/write register
SADR[7:0]: 00001001₂
REFH[7:0] resets to 00000000₂
reserved - Refresh row field.
This field contains the high-order bits of the row address that
will be refreshed during the next refresh interval. This row
address will be incremented after a REFI command for auto-
refresh, or when the BANK[2:0] field for the REFB register
equals the maximum bank address for self-refresh.
Figure 25 : Refresh Middle (REFM) Row Register
76543210
reserved
R[11:8]
Refresh Middle Row Register
Read/write register
SADR[7:0]: 00001010₂
REFM[7:0] resets to 00000000₂
R[11:8] - Refresh row field.
This field contains the middle-order bits of the row address that
will be refreshed during the next refresh interval. This row
address will be incremented after a REFI command for auto-
refresh, or when the BANK[2:0] field for the REFB register
equals the maximum bank address for self-refresh.
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Rev. 1.1 August 2006