K4Y50164UC Datasheet, PDF (50/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
10.8 Sub-Row (Sub-Page) Sensing
The SP[1:0] field of the CFG register controls what fraction of a row is sensed during a ROWA activate operation. This permits the con-
troller to reduce the amount of power consumed by normal transactions if a smaller row size can be tolerated by the application. Note
that the REFA and REFI activate operations always sense the full row, the SP[1:0] setting does not affect these operations. Refresh
operations during Powerdown are likewise unaffected by the SP[1:0] setting.
The permissible values of the SP[1:0] field are affected by the value programmed into the WIDTH[2:0] field of the CFG register. The table
in the following figure summarizes the allowed combinations of values.
In general the value of WIDTH[2:0] is chosen, and this then limits the possible values of SP[1:0] that can be used, as seen by the table in
the figure above. In other words, the combinations indicated by the gray boxes labeled “NO” may not be used, since this would allow
accessing of sense amplifier cells with invalid data.
If half-row activation is selected (with SP[1:0] = 01), then the value of SR[1] used in the ROWA packet for activation must be the same as
the value of SC[1] used in the COL/COLM packet for a read/write access.
XDR DRAM device will operate in half-activation mode, even when programmed for quarter-activation (with SP[1:0] = 10).
Figure 49 Sub-Row Example
Allowed combinations of
WIDTH[2:0]
WIDTH[2:0]
SP[1:0]
x2
x4
x8
x16
SP[1:0]
SC[3:0]
001
010
010
010
SR[1:0]
full 00 OK
OK
OK
OK
half 01 OK
NO
NO
NO
allowed
SR[1:0]
values for
each SP[1:0]
combination
xx
0x,1x
allowed
SC[3:0]
values for
each WIDTH
combination
000x
001x
010x
011x
100x
101x
110x
111x
00xx
01xx
10xx
11xx
0xxx
1xxx
xxxx
NOTE - for half-activation, the
following relationship must be
observed : SR[1]=SC[1]
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Rev. 1.1 August 2006