K4Y50164UC Datasheet, PDF (66/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
14.4 DRSL DQ Transmit Timing
Figure60 shows a timing diagram for transmitting read data on the DQ15...0/DQN15...0 data pins of the memory component. This
diagram represents a magnified view of these pins and only a few clock cycles are shown (CFM and CFMN are the clock signals).
Timing events are measured to and from the primary CFM/CFMN crossing point in which CFM makes its high-voltage-to-low-voltage
transition. The DQ15...0/DQN15...0 signals are high-true: a low voltage represents a logical zero and a high voltage represents a logical
one. They are also differential - timing events on the DQ15...0/DQN15...0 pins are measured to and from the point that each differential
pair crosses.
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. The rise (t_{OR, DQ}) and fall
time (t_{OF, DQ}) of the signals are measured from the 20% and 80% points of the full-swing levels.
20% = V_OL, _DQ + 0.2*(V_OH, _DQ - V_OL, _DQ)
80% = V_OL, _DQ + 0.8*(V_OH, _DQ - V_OL, _DQ)
There are 16 data transmit windows defined for each DQ15...0/DQN15...0 pin pair. The transmitting windows for a particular DQi/DQNi
pin pair is referenced to an offset parameter t_QOFF,_DQi (the index “i” may take on the values {0, 1, .., 15} and refers to each of the DQ15...
0/DQN15...0 pin pairs).
The t_QOFF,_DQi + t_Q,_DQ,MAX expression determines the time between the primary CFM/CFMN crossing point and the offset point for the
DQi/DQNi pin pair.
The offset values t_QOFF,_DQi for each of the 16 DQi/DQNi pin pairs can be different. However, each is constrained to lie inside the range
{t_QOFF,_MIN, t_QOFF,_MAX}. Furthermore, each offset value t_QOFF,_DQi is static; its value will not change during system operation. Its value can
be determined at initialization time.
The 16 transmit windwos (j = 0 ... 15} for the first pair DQ0/DQN0 are labeled “0” through “15”. Each window begins at the time
(t_QOFF,_DQ0 + t_Q,_DQ,MAX +((j+0.5)/8)*t_CYCLE) and ends at the time (t_QOFF,_DQ0 + t_Q,_DQ,MIN +((j+1.5)/8)*t_CYCLE) measured after the primary
CFM/CFMN crossing point.
The 16 transmit windwos (j = 0 ... 15} for the other pair DQi/DQNi are also labeled “0” through “15”. Each window begins at the time
(t_QOFF,_DQi + t_Q,_DQ,MAX +((j+0.5)/8)*t_CYCLE) and ends at the time (t_QOFF,_DQi + t_Q,_DQ,MIN +((j+1.5)/8)*t_CYCLE) measured after the primary
CFM/CFMN crossing point.
Note that when no read data is to be transmitted on the DQ/DQN pins(and no other component is transmitting on the external DQ/DQN
wires), then the voltage level on the DQ/DQN pins will follow the voltage reference value VTERM,DRSL on the VTERM pin. The logical
value of each DQ/DQN pin pair in this no-drive state will be “1/1”; when read data is driven, each DQ/DQN pin pair will have either the
logical value of “1/0” or “0/1”.
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Rev. 1.1 August 2006