K4Y50164UC Datasheet, PDF (41/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
Figure 38 : PLL0 Register
76543210
reserved
PLL0 Register
SADR[7:0]: 00011010₂
TBD
Read/write register
PLL0[7:0] resets to 00000000₂
Figure 39 : PLL1 Register
76543210
reserved
PLL1 Register
SADR[7:0]: 00011011₂
TBD
Read/write register
PLL1[7:0] resets to 00000000₂
Figure 40 : IFT Register
76543210
reserved
IFT Register
SADR[7:0]: 00011100₂
TBD
Read/write register
IFT[7:0] resets to 00000000₂
Figure 41 : DA Register
76543210
reserved
DA Register
SADR[7:0]: 00011101₂
TBD
Read/write register
DA[7:0] resets to 00000000₂
7654
CWD[3:0]
Figure 42 : Delay (DLY) Control Register
3210
CAC[3:0]
DLY Register
SADR[7:0]: 00011111₂
Read/write register
DLY[7:0] resets to 00110110₂
CAC[3:0] - Programmed value of t_CAC timing parameter:
0110₂ - t_CAC = 6*t_CYCLE 1000₂ - t_CAC = 8*t_CYCLE
0111₂ - t_CAC = 7*t_CYCLE others - Reserved.
CWD[3:0] - Programmed value of t_CWD timing parameter:
0011₂ - t_CWD = 3*t_CYCLE
0100₂ - t_CWD = 4*t_CYCLE others - Reserved.
Figure 43 : Partner-Definable (PART0-PARTF) Registers
76543210
reserved
PART0 Register
SADR[7:0]: 10000000₂
Read/write register
PART0[7:0] resets to 00000000₂
76543210
reserved
PART1 Register
SADR[7:0]: 10000001₂
Read/write register
PART1[7:0] resets to 00000000₂
76543210
reserved
PARTF Register
SADR[7:0]: 10001111₂
Read/write register
PARTF[7:0] resets to 00000000₂
Note - The partner-definable registers should not be written or read; doing so will produce undefined results.
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Rev. 1.1 August 2006