K4Y50164UC Datasheet, PDF (45/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
10.4 Power State Management
Figure46 shows power state transition diagrams for the XDR DRAM device. There are two power states in the XDR DRAM: Powerdown
and Active. Powerdown state is to be used in applications in which it is necessary to shut down the CFM/CFMN clock signals. In this
state, the contents of the storage cells of the XDR DRAM will be retained by an internal state machine which performs periodic refresh
operations using the REFB and REFr control registers.
The upper diagram shows the sequence needed for Powerdown entry. Prior to starting the sequence, all banks of XDR DRAM must be
precharged so they are left in a closed state. Also, all 2³ banks must be refreshed using the current value of the REFr registers, and the
REFr registers must not be incremented with the REFI command at the end of this special set of refresh transactions. This ensures that
no matter what value has been left in the REFB register, no row of any bank will be skipped when automatic refresh is first started in
Powerdown. There may be some banks at the current row value in the REFr registers that are refreshed twice during the Powerdown
entry process.
After the last request packet (with the command CMDa in the upper diagram of the figure), an interval of t_CMD-PDN is observed. No
request packets should be issued during this period.
A COLX packet with the PDN command is issued after this interval, causing the XDR DRAM to enter Powerdown state after an interval
of t_PDN-ENTRY has elapsed (this is the parameter that should be used for calculating the power dissipation of the XDR DRAM). The CFM/
CFMN clock signals may be removed a time t_PDN-CFM after the COLX packet with the PDN command. Also, the termination voltage
supply may be removed (set to the ground reference) from the Vterm pins a time t_PDN-CFM after the COLX pakcet with the PDN
command. The voltage on the DQ/DQN pins will follow the voltae on the Vterm pins during Powerdonwn entry.
When the XDR DRAM is in Powerdown, an internal frequency source and state machine will automatically generate internal refresh
transactions. It will cycle through all 2³ state combinations of the REFB register. When the largest value is reached and the REFB value
wraps around, the REFr register is incremented to the next value. The REFB and REFr values select which bank and which row are
refreshed during the next automatic refresh transaction.
The lower diagram shows the sequence needed for Powerdown exit. The sequence is started with a serial broadcast write (SBW
command) transaction using the serial bus of the XDR DRAM. This transaction writes the value “00000001” to the Power Management
(PM) register (SADR = “00000011”) of all XDR DRAMs connected to the serial bus. This sets the PX bit of the PM register, causing the
XDR DRAMs to return to Active power state.
The CFM/CFMN clock signals must be stable a time t_CFM-PDN before the end of the SBW transaction. Also, the termination voltage
supply must be restored to its normal operating point (V_TERM,DRSL) on the Vterm pins a time t_CFM-PDN before the end of the SWB trans-
action. The voltage on the DQ/DQN pins will follow the voltage on the Vterm pins during Powerdown exit.
The XDR DRAM will enter Active state after an interval of t_PDN-EXIT has elapsed from the end of the SBW transaction (this is the param-
eter that should be used for calculating the power dissipation of the XDR DRAM).
The first request packet may be issued after an interval of t_PDN-CMD has elapsed from the end of the SBW transaction, and must contain
a “REFA” command in a ROWP packet. In this example, this packet is denoted with the command “REFA 1”. No other request packets
should be issued during this t_PDN-CMD interval.
All “n” banks (in the example, n=2³) must be refreshed using the current value of the REFr registers. The “nth” refresh transaction will
use a “REFI” command to inrement the REFr register (instead of a “REFR” command). This ensures that no matter what value has been
left in the REFB register, no row of any bank will be skipped when normal refresh is restarted in Active state. There may be some banks
at the current row value in the REFr registers that are refreshed twice during the Powerdown exit process.
Note that during the Powerdown state an internal time source keeps the device refreshed. However, during the t_PDN-CMD interval, no
internal refresh operations are performed. As a result, an additional burst of refresh transactions must be issued after the burst of “n”
transactions described above. This second burst consists of “m” refresh transactions:
m = ceiling[2³*2¹²*t_PDN-CMD/t_REF]
Where “2¹²â€ is the number of rows per bank, and “2³â€ is the number of banks. Every ”nth” refresh transaction (where n=2³) will use a
“REFI” command (to increment the REFr register) instead of a “REFA” command.
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Rev. 1.1 August 2006