K4Y50164UC Datasheet, PDF (68/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
14.5 Serial Interface Receive Timing
Figure61shows a timing diagram for the serial interface pins of the memory component. This diagram represents a magnified view of the
pins only a few clock cycles.
The serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage represents a logical one.
Timing events are measured to and from the V_REF,RSL level. Because timing intervals are measured in this fashion, it is necessary to
constrain the slew rate of the signals. The rise time (t_R,SCK and t_RI,SI) and fall time (t_F,SCK and t_IF,_SI) of the signals are measured from the
20% and 80% points of the full-swing levels.
20% = V_IL,_SI + 0.2 *(V_IH,_SI - V_IL,_SI)
50% = V_IL,_SI + 0.5 *(V_IH,_SI - V_IL,_SI)
80% = V_IL,_SI + 0.8 *(V_IH,_SI - V_IL,_SI)
There is one receiving window defined for each serial interface signal (RST, CMD and SDI pins). This window has a set time (t_{S, RQ}) and
a hold time (t_{H, RQ}) measured around the falling edge of the SCK clock signal.
Figure 61 : Serial Interface Receive Waveforms
SCK
t_L,SCK
t_CYC,SCK
t_H,SCK
t_F,SCK
t_R,SCK
logic 0
V_IH,SI
80%
V_REF,RSL
20%
V_IL,SI
logic 1
RST
CMD
SDI
t_S,SI
t_H,SI
t_IR,SI
t_IF,SI
logic 0
V_IH,SI
80%
V_REF,RSL
20%
V_IL,SI
logic 1
68 of 76
Rev. 1.1 August 2006