K4Y50164UC Datasheet, PDF (61/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
13.4 Timing Parameters
Table18 summarizes the timing parameters that characterize the core logic of this memory component.. These timing parameters will
vary as a function of the component’s speed bin. The four sections deal with the timing intervals between packets with, respectively, row-
row commands, row-column commands, column-column commands, and column-row commands.
Table 18 : Timing Parameters
Symbol
Parameter and Other Conditions
Min Min Min
(A)
(B) (C)
Units
Figure(s)
t_RC
t_RAS
Row-cycle time: interval between successive ROWA-
ACT or ROWP-REFA or ROWP-REFI activate com-
mands to the same bank.
t_RC
t_{RC-R, 2tCC} = t_RCD-R + t_CC+ t_RDP + t_RPa
t_{RC-W, 2tCC, noERAW} = t_RCD-W + t_CC+ t_WRP +t_RPa
16
16
19
t_{RC-W, 2tCC, ERAW} = t_RCD-W + t_CC+ t_WRP + t_RPa
23
Row-asserted time: interval between a ROWA-ACT or ROWP-REFA or ROWP-REFI activate command
and a ROWP-PRE or ROWP-REFP precharge command to the same bank.
10
Note that t_RAS,MAX is 64 us for all timing bins.
t_RP
Row-precharge time: interval between a ROWP-PRE or ROWP-REFP precharge command and a ROWA-
ACT or ROWP-REFA or ROWP-REFI activate command to the same bank.
6
t_PP
Precharge-to-precharge time: interval between suc-
cessive ROWP-PRE or ROWP-REFP precharge com-
mands to different banks.
t_PP
t_PP-Db
4
1
t_RR
Row-to-row time: interval between ROWA-ACT or
ROWP- REFA or ROWP-REFI activate commands to
different banks.
t_RR
t_RR-Dc
4
4
t_RCD-R
Row-to-column-read delay: interval between a ROWA-ACT activate command and a COL-RD read com-
mand to the same bank.
5
t_RCD-W
Row-to-column-write delay: interval between a ROWA-ACT activate command and a COL-WR or COL-
WRM write command to the same bank.
1
t_CAC
Column access delay: interval from COL-RD read command to Q read data
6
t_CWD
Column write delay: interval from a COL-WR or COLM-WRM write command to D write data.
3
t_CC
Column-to-column time: interval between successive COL-RD commands, or between successive COL-
WR or COLM-WRM commands.
2
t_RW-BUB,
XDRDRAM
Read-to-write bubble time: interval between the end of a Q read data packet and the start of D write data
packet (the end of a data packet is the time interval t_CC after its start).
3
t_WR-BUB,
XDRDRAM
Write-to-read bubble time: interval between the end of a D writed data and the start of Q read data packet
(the end of a data packet is the time interval t_CC after its start).
3
t_∆RW
Read-to-write time: interval between a COL-RD read command and a COL-WR or COLM-WRM write com-
mand.^d
8
t_∆WR
Write-to-read time: interval between a COL-WR or
COLM-WRM write command and a COL-RD read com-
mand.
t_∆WR
t_∆WR-De
9
2
t_RDP
Read-to-precharge time: interval between a COL-RD read command and a ROWP-PRE precharge com-
mand to the same bank.
3
t_WRP
Write-to-precharge time: interval between a COL-WR or COLM-WRM write command and a ROWP-PRE
precharge command to the same bank.
10
t_DR
Write data-to-read time: interval between the start of D write data and a COL-RD read command to the
same bank.
6
t_DP
Write data-to-precharge time: interval between D write data and ROWP-PRE precharge command to the
same bank.
7
t_{LRRn-LRRn Interval between ROWP-LRRn command and a subsequent ROWP-LRRn command.} ^f
16
t_REFx-LRRn Interval between ROWP-REFx command and a subsequent ROWP-LRRn command.
16
t_LRRn-REFx Interval between ROWP-LRRn command and a subsequent ROWP-REFx command.
16
20
24
20
24
24
24
28
28
13
17
7
7
4
4
1
1
4
4
4
4
7
7
3
3
7
7
3
3
2
2
3
3
3
3
9
9
10
10
2
2
4
4
12
12
7
7
9
9
20
24
20
24
20
24
t_CYCLE
Figure 4 -
Figure 7
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
Figure 4 -
Figure 7
Figure 4 -
Figure 7
Figure 4 -
Figure 7
Figure 4 -
Figure 7
Figure 4 -
Figure 7
Figure 4 -
Figure 7
Figure 10
Figure 9
Figure 4 -
Figure 7
Figure 13
Figure 13
Figure 12
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
Figure 12
Figure 4 -
Figure 7
Figure 4 -
Figure 7
Figure 12
Figure 9
Table5
Table5
Table5
a. The t_RC,MIN parameter is applicable to all transaction types (read, write, refresh, etc.). Read and write transactions may have an additional limitation, depending upon
how many column accesses (each requiring t_CC) are performed in each row access (t_RC). The table lists the special cases (t_{RC-R, 2tCC}, t_{RC-W, 2tCC, noERAW}, t_{RC-W, 2tCC,}
ERAW^{) in which two column accesses are performed in each row access. Note that t}RC-W, 2tCC, ERAW ^{uses a relaxed value of t}RCD-W ^{that is equal to t}RCD-R,MIN^{. All}
other parameters are minimum.
b. t_PP-D is the t_PP parameter for precharges to different bank sets. See “Simultaneous Precharge” on page 56.
c. t_RR-D is the t_RR parameter for activates to different bank sets. See “Simultaneous Activation” on page 55.
d. See “Propagation Delay” on page 32.
e. t_∆WR-D is the t_∆WR parameter for write-read accesses to different bank sets. See “Multiple Bank Sets and the ERAW Feature” on page 53. Also, note that the value of
t_∆WR-D may not take on the values {3,5,7} within the range{t_{∆WR-D,MIN}, ... t_∆WR,MIN-1}. t_DWR-D may assume any value ≥ t_∆WR,MIN.
f.ROWP-LRRn includes the commands {ROWP-LRR0,ROWP-LRR1,LOWP-LRR2}, ROWP-REFx includes the commands {ROWP-REFA,ROWP-REFI, LOWP-REFP},
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Rev. 1.1 August 2006