K4Y50164UC Datasheet, PDF (11/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
6.0 Block Diagram
A block diagram of the XDR DRAM device is shown in Figure2. It shows all interface pins and major internal blocks.
The CFM and CFMN clock signals are received and used by the clock generation logic to produce three virtual clock signals : 1/t_CYCLE,
2/t_CYCLE, and 16/t_CC. The frequency of these signals are 1x, 2x, and 8x that of the CFM and CFMN signals. These virtual signals show
the effective data rate of the logic blocks to which they connect; they are not necessarily present in the actual memory component.
The RQ11 ... RQ0 pins receive the request packet. Two 12-bit words are received in one t_CYCLE interval. This is indicated by the 2/t_CYCLE
clocking signal connected to the 1:2 Demux Block that assembles the 24-bit request packet. These 24bits are loaded into a regis-
ter(clocked by the 1/t_CYCLE clocking signal) and decoded by the Decode Block. The V_REF pin supplies a reference voltage used by the
RQ receivers.
Three sets of control signals are produced by the Decode Block. These include the bank(BA) and row(R) addresses for an activate(ACT)
command, the bank(BR) and row(REFr) addresses for a refresh activate(REFA) command, the bank(BP) address for a precharge(PRE)
command, the bank(BR) adddress for a refresh precharge(REFP) command, and the bank(BC) and column(C and SC) addresses for a
read(RD) or write(WR or WRM) command. In addition, a mask(M) is used for a masked write(WRM) command.
These commands can all be optionally delayed in increments of t_CYCLE under control of delay fields in the request. The control signals of
the commands are loaded into registers and presented to the memory core. These registers are clocked at maximum rates determined
by core timing parameters, in this case 1/t_RR, 1/t_PP, and 1/t_CC(1/4, 1/4, and 1/2 the frequency of CFM in the -3200 component). These
registers may be loaded at any t_CYCLE rising edge. Once loaded, they should not be changed until a t_RR, t_PP, or t_CC time later because
timing paths of the memory core need time to settle.
A bank address is decoded for an ACT command. The indicated row of the selected bank is sensed and placed into the associated sense
amp array for the bank. Sensing a row is also referred to as “Opening a page”for the bank.
Another bank address is decoded for a PRE command. The indicated bank and associated sense amp array are precharged to a state in
which a subsequent ACT command can be applied. Precharging a bank is also called “closing the page” for the bank.
After a bank is given an ACT command and before it is given a PRE command, it may receive read(RD) and write(WR) column commands.
These commands permit the data in the bank’s associated sense amp array to be accessed.
For a WR command, the bank address is decoded. The indicated column of the associated sense amp array of the selected bank is written
with the data received from the DQ15 ... DQ0 pins.
The bank address is decoded for a RD command. The indicated column of the selected bank’s associated sense amp array is read. The
data is transmitted onto the DQ15 ... DQ0 pins.
The DQ15 ... DQ0 pins receive the write data packet(D) for a write transaction. 16 sixteen-bit words are received in one t_CC interval. This
is indicated by the 16/t_CC clocking signal connected to the 1:16 Demux Block that assembles the 16x16-bit write data packet. The write
data is then driven to the selected Sense Amp Array Bank.
16 sixteen-bit words are accessed in the selected Sense Amp Array Bank for a read transaction. The DQ15 ... DQ0 pins transmit the read
data packet(Q) in one t_CC interval. This is indicated by the 16/t_CC clocking signal connected to the 16:1 Mux Block. The V_TERM pin supplies
a termination voltage for the DQ pins.
The RST, SCK, and CMD pins connect to the Control Register block. These pins supply the data, address and conrol needed to write the
control registers. The read data for these registers is accessed through the SDO/SDI pins. These pins are also used to initialize the device.
The control registers are used to transition between power modes, and are also used for calibrating the high speed transmit and receive
circuits of the device. The control registers also supply bank(REFB) and row(REFr) address for refresh operations.
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Rev. 1.1 August 2006