K4Y50164UC Datasheet, PDF (37/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
Figure 18 : Configuration (CFG) Register
76543210
Configuration Register
Read/write register
SP[1:0] rsrv ^SLE rsrv
WIDTH[2:0]
SADR[7:0]: 00000010₂
CFG[7:0] resets to 00000100₂
WIDTH[2:0] - Device interface width field.
SLE - Serial Load enable field.
0₂ - WDSL-path-to-memory disabled
1₂ - WDSL-path-to-memory enabled
000₂ - Reserved.
001₂ - x2 device width
010₂ - x4 device width
011₂ - x8 device width
100₂ - x16 device width
101₂, 110₂, 111₂ - Reserved
SP[1:0] - Sub page activation field.(used with SR[1:0]field in ROWA packet)
00₂ - Full Page Activation (x16,x8,x4 and x2 WIDTH)
01₂ - Half Page Activation (x2 WIDTH only)
10₂ - Reserved
11₂ - Reserved
Figure 19 : Power Management (PM) Register
765
PST[1:0]
432
reserved
10
PX
Power Management Register
SADR[7:0]: 00000011₂
Read/write register
PM[7:0] resets to 00000000₂
PX - Powerdown exit field.(write-one-only, read=zero)
0₂ - Powerdown entry - do not write zero - use PDN command
1₂ - Powerdown exit - write one to exit
PST[1:0] - Power state field (read-only).
00₂ - Powerdown (with self-refresh)
01₂ - Active/active-idle
10₂ - reserved
11₂ - reserved
Figure 20 : Write Data Serial Load (WDSL) Control Register
76543210
WDSD[7:0]
Write Data Serial Load Control Register Read/write register
SADR[7:0]: 00000100₂
WDSL[7:0] resets to 00000000₂
WDSD[7:0] - Writing to this register places eight bits of data into
the serial-to-parallel conversion logic (the “Demux” block of
Figure 2). Writing to this register “2x16” times accumulates a full
“t_CC” worth of write data. A subsequent WR command (with
SLE=1 in CFG register in Figure 36) will write this data (rather
than DQ data) to the sense amps of a memory bank. The shift-
ing order of the write data is shown in Table 11.
Figure 21 : RQ Scan High (RQH) Register
76543210
reserved
RQH[3:0]
RQ Scan High Register
SADR[7:0]: 00000110₂
Read/write register
RQH[7:0] resets to 00000000₂
RQH[3:0] - Latched value of RQ[11:8] in RQ wire test mode.
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Rev. 1.1 August 2006