K4Y50164UC Datasheet, PDF (10/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
5.0 Pin Description
XDR^TM DRAM
Table2 summarizes the pin functionality of the XDR DRAM device. The first group of pins provide the necessary supply voltages. These
include V_DD and GND for the core and interface logic, V_REF for receiving input signals, and V_TERM for the driving output signals.
The next group of pins are used for high bandwidth memory accesses. These include DQ15 ... DQ0 and DQN15 ... DQN0 for carrying
read and write data signals, RQ11 ... RQ0 for carrying request signals, and CFM and CFMN for carrying timing information used by the
DQ, DQN and RQ signals.
The final set of pins comprise the serial interface that is used for control register accesses. These include RST for initializing the state of
the device, CMD for carrying command signals, SDI and SDO for carrying register read data, and SCK for carrying the timing information
used by the RST, SDI, SDO, and CMD signals.
Table 2 : Pin Description
Signal
I/O
Type
No. of pins
Description
V_DD
GND
V_REF
V_TERM
DQ15..0^b
DQN15..0^b
RQ11..0
CFM
-
-
-
-
-
-
-
-
I/O
DRSL^a
I/O
DRSL^a
I
RSL^a
I _DIFFCLK^a
CFMN
RST
CMD
I _DIFFCLK^a
I
RSL^a
I
RSL^a
SCK
I
RSL^a
SDI
I
RSL^a
SDO
O
CMOS^a
RSRV^b
-
-
Total pin count per package
22
Supply voltage for the core and interface logic of the device.
24
Ground reference for the core and interface logic of the device.
1
Logic threshold reference voltage for RSL signals.
4
Termination voltage for DRSL signals.
16^b
Positive data signals that carry write or read data to and from the device.
16^b
Negative data signals that carry write or read data to and from the device.
12
Request signals that carry control and address information to the device.
1
Clock from master — Positive interface clock used for receiving RSL signals, and
receiving and transmitting DRSL signals from the Channel.
1
Clock from master — Negative interface clock used for receiving RSL signals, and
receiving and transmitting DRSL signals from the Channel.
1
Reset input — This pin is used to initialize the device.
1
Command input — This pin carries command, address, and control register write
data into the device.
1
Serial clock input — Clock source used for reading from and writing to the control
registers.
1
Serial data input — This pin carries control register read data through the device.
This pin is also used to initialize the device.
1
Serial data output — This pin carries control register read data from the device. This
pin is also used to initialize the device.
2^b
Reserved pins — Follow Rambus XDR system design guidelines for connecting
RSRV pins
104
a. All DQ and CFM signals are high-true; low voltage is logic 0 and high voltage is logic 1.
All DQN, CFMN, RQ, RSL, and CMOS signals are low-true; high voltage is logic 0 and low voltage is logic 1.
b. The number of DQ pins changes by I/O configuration. See the table below.
x16
x8
x4
x2
Singnal
DQ15...0
DQN15...0
RSRV
No. of pins Singnal
16
DQ7...0
16
DQN7...0
2
RSRV
No. of pins Singnal
8
DQ3...0
8
DQN3...0
18
RSRV
No. of pins Singnal
4
DQ1...0
4
DQN1...0
26
RSRV
No. of pins
2
2
30
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Rev. 1.1 August 2006