K4Y50164UC Datasheet, PDF (12/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
Figure 2 : 512Mb (8x4Mx16) XDR DRAM Block Diagram
RQ11..0
12
VREF
1
CFM CFMN
RST,SCK,CMD,SDI SDO
4
1
XDR^TM DRAM
2/t_CYCLE
12
12
COL logic
1:2 Demux
12
reg
12
Decode
PRE logic ACT logic
1/t_CYCLE
1/t_CYCLE
2/t_CYCLE
16/ t_CC
REFB,REFr
7 6+4 3 3
12 3
Control Registers
Power Mode Logic
Calibration Logic
Refresh Logic
Initialization Logic
WIDTH
RD,WR
delay
{0..1}*t_CYCLE
PRE delay
{0..3}*t_CYCLE
ACT delay
{0..1}*t_CYCLE
1/t_RR
2³
BA,BR,REFB ³
R,REFr ¹²
1/t_PP
2³
BP,BR,REFB ³
1
ACT
1
ACT
ROW
ROW
1
PRE
1
PRE
Bank Array
1^B6^ax^nk16⁰*2⁶*2¹²
16x16*2⁶
Bank 0
Bank (2³ - 1)
16x16*2⁶
1/t_CC
2³
BC
3
C
6
SC
4
M
8
1
R/W
1
R/W
COL
COL
Sense Amp Array
16x16*2⁶
Sense Amp 0
Sense Amp (2³ - 1)
16x16
S[15:0][15:0]
16x16
16x16
Byte Mask (WR)
16x16
WIDTH
Width Demux (WR)
Width Mux (RD)
16x16
D[15:0][15:0]
Q[15:0][15:0] 16x16
1:16 Demux
16
termination
16
16/t_CC
16:1 Mux
16
16
16/t_CC
2
VTERM
16
DQ15..0
16
DQN15..0
12 of 76
Rev. 1.1 August 2006