K4Y50164UC Datasheet, PDF (31/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
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K4Y50044UC
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XDR^TM DRAM
8.4 Read/Write Interaction
The previous section described overlapped read transactions and overlapped write transactions in isolation. This section will describe
the interaction of read and write transactions and the spacing required to avoid channel and core resource conflicts.
Figure12 shows a timing diagram (top) for the first case, a write transaction followed by a read transaction. Two COL packets with WR
commands are presented on cycles T₀ and T₂. The write data packets are presented a time t_CWD later on cycles T₄ and T₆. The device
requires a time t_∆WR after the second COL packet with a WR command before a COL packet with a RD command may be presented.
Two COL packets with RD commands are presented on cycles T₁₁ and T₁₃. The read data packets are returned a time t_CAC later on
cycles T₁₇ and T₁₉. The time t_∆WR is required for turning around internal bi-directional interconnections (inside the device). This time
must be observed regardless of whether the write and read commands are directed to same banks or different banks. A gap t_WR-
BUB^,XDRDRAM ^{will appear on the DQ bus between the end of the D(a2) packet and the beginning of the Q(b1) packet (measured at the}
appropriate packet reference points). The size of this gap can be evaluated by calculating the difference between cycles T₂ and T₁₇
using the two timing paths :
t_WR-BUB, _XDRDRAM = t_∆WR + t_CAC - t_CWD - t_CC
In this example, the value of t_WR-BUB,_XDRDRAM is greater than its minimum value of t_WR-BUB,_XDRDRAM,MIN. The values of t_∆WR and t_CAC
are equal to their minimum values.
In the second case, the timing diagram displayed at the bottom of Figure12 illustrates a read transaction followed by a write transaction.
Two COL packets with RD commands are presented on cycles T₀ and T₂. The read data packets are returned a time t_CAC later on cycles
T₆ and T₈. The device requires a time t_∆RW after the second COL packet with a RD command before a COL packet with a WR command
may be presented. Two COL packets with WR commands are presented on cycles T₁₀ and T₁₂. The write data packets are presented a
time t_CWD later on cycles T₁₃ and T₁₅. The time t_∆RW is required for turning around the external DQ bi-directional interconnections
(outside the device). This time must be observed regardless whether the read and write commands are directed to the same banks or
different banks. The time t_∆RW depends upon four timing parameters. and may be evaluated by calculating the difference between cycles
T₂ and T₁₃ using the two timing paths :
t_∆RW + t_CWD = t_CAC + t_CC + t_RW-BUB, _XDRDRAM or t_∆RW = (t_CAC - t_CWD) + t_CC + t_RW-BUB, _XDRDRAM
In this example, the values of t_∆RW, t_CAC, t_CWD, t_CC, and t_RW-BUB, _XDRDRAM are equal to their minimum values.
Figure 12 : Write/Read Interaction
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
T₀ T₁
WR
a1
T₂ T₃ T₄
WR ^tCWD
a2
D(a1)
t_CWD
T₅ T₆ T₇
t_∆WR
D(a2)
t_CC
T₈ T₉
t_DR
T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
RD
RD
b1
b2 _tCAC
t_{WR-BUB,XDRDRAM}
t_CYCLE
Q(b1)
Q(b2)
Transaction a: WR
Transaction b: RD
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
Write/Read Turnaround Example
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
T₀ T₁
RD
a1
T₂ T₃ T₄
RD
a2
t_CAC
T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
t_∆RW
Q(a1)
WR
b1
Q(a2)
WR
b2 _tCWD
D(b1)
D(b2)
t_CYCLE
t_CC t_{RW-BUB,XDRDRAM}
Transaction a: WR
Transaction b: RD
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
b1 = {Bb,Cb1}
b2 = {Bb,Cb2}
Read/Write Turnaround Example
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Rev. 1.1 August 2006