K4Y50164UC Datasheet, PDF (47/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

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XDR^TM DRAM
10.5 Initialization
Figure47 shows the topology of the serial interface signals of a XDR DRAM system. The three signals RST, CMD, and SCK are trans-
mitted by the controller and are received by each XDR DRAM device along the bus. The signals are terminated to the V_TERM supply
through termination components at the end farthest from the controller. The SDI input of the XDR DRAM device furthest from the
controller is also terminated to V_TERM. The SDO output of each XDR DRAM device is transmitted to the SDI input of the next XDR
DRAM device (in the direction of the controller). This SDO/SDI daisy chain topology continues to the controller, where it ends at the SRD
input of the controller. All the serial interface signals are low-true. All the signals use RSL signaling circuits, except for the SDO output
which uses CMOS signaling circuits.
Figure 47 : Serial Interface Systems Topology
VTERM
RST CMD SCK
RST CMD SCK
RST CMD SCK
RST CMD SCK
SRD
SDO
SDI
...
SDO
SDI
...
SDO
SDI
Controller
XDR DRAM [63]
XDR DRAM [j]
XDR DRAM [0]
Figure48 shows the initialization timing of the serial interface for the XDR DRAM [k] device in the system shown above. Prior to initializa-
tion, the RST is held at zero. The CMD input is not used here, and should also be held at zero. Note that the inputs are all sampled by
the negative edge of the SCK clock input. The SDI input for the XDR DRAM[0] device is zero, and is unknown for the remaining devices.
On negative SCK edge S₈ the RST input is sampled one. It is sampled one on the next four edges, and is sampled zero on edge S₁₂ a
time t_RST-10 after it was first sampled one. The state of the control registers in the XDR DRAM device are set to their reset values after
the first edge (S₈) in which RST is sampled one.
Figure 48 : Initialization Timing for XDR DRAM [k] Device
S₀ S₂ S₄ S₆ S₈ S₁₀ S₁₂ S₁₄ S₁₆ S₁₈ S₂₀ S₂₂ S₂₄ S₂₆ S₂₈ S₃₀ S₃₂ S₃₄ S₃₆ S₃₈ S₄₀ S₄₂ S₄₄ S₄₆ S₄₈
SCK
RST
CMD
t_RST-10
t_CYC,SCK
‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
t_RST-SDI,00 = k * t_CYC,SCK
SDI
(input)
SDO
(output)
‘x’ ‘x’ ‘x’ ‘x’ ‘x’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
t_RST-SDO,11
t_SDI-SDO,00
‘x’ ‘x’ ‘x’ ‘x’ ‘x’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
The SDI inputs will be sampled one within a time t_RST-SDO,₁₁ after RST is first sampled one in all the XDR DRAMs except for XDR DRAM
[0]. XDR DRAM [0]’s SDI input will always be sampled zero.
XDR DRAM [k] will see its RST input sampled zero at S₁₂, and will then see its SDI input sampled zero at S₁₆ (after SDI had previously
been sampled one). This interval (measured in t_CYC,SCK units) will be equal to the index [k] of the XDR DRAM device along the serial
interface bus. In this example, k is equal to 4.
This is because each XDR DRAM device will drive its SDO output zero around the SCK edge a time t_SDI-SDO,₀₀ after its SDI input is
sample zero.
In other words, the XDR DRAM [0] device will see RST and SDI both sampled zero on the same edge S₁₂ (t_RST-SDI,₀₀ will be 0 *t_CYC,SCK
units), and will drive its SDO to zero around the subsequent edge (S₁₃).
The XDR DRAM [1] device will see SDI sampled zero on edge S₁₃ (t_RST-SDI,₀₀ will be 1*t_CYC,SCK units), and will drive its SDO to zero
around the subsequent edge (S₁₄).
The XDR DRAM [2] device will see SDI sampled zero on edge S₁₄ (t_RST-SDI,00 will be 2* t_CYC,SCK units), and will drive its SDO to zero
around the subsequent edge (S₁₅).
47 of 76
Rev. 1.1 August 2006