K4Y50164UC Datasheet, PDF (25/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
8.0 Memory Operations
8.1 Write Transactions
Figure9 shows four examples of memory write transactions. A transaction is one or more request packets (and the associated data
packets) needed to perform a memory access. The state of the memory core and the address of the memory access determine how
many request packets are needed to perform the access.
The first timing diagram shows a page-hit write transaction. In this case, the selected bank is already open (a row is already present in
the sense amp array for the bank). In addition, the selected row for the memory access matches the address of the row already sensed
(a page hit). This comparison must be done in the memory controller. In this example, the access is made to row Ra of bank Ba.
In this case, write data may be directly written into the sense amp array for the bank, and row operations(activated or precharge) are not
needed. A COL packet with WR command to column Ca1 of bank Ba is presented on edge T₀, and a second COL packet with WR
command to column Ca1 of bank Ba is presented on edge T₂. Two write data packets D(a1) and D(a2) follow these COL packets after
the write data delay t_CWD. The two COL packets are separated by the column-cycle time t_CC. This is also the length of each write data
packet.
The second timing diagram shows an example of a page-miss write transaction. In this case, the selected bank is already open (a row is
already present in the sense amp array for the bank). However, the selected row for the memory access does not match the address of
the row already sensed (a page miss). This comparsion must be done in the memory controller. In this example, the access is made to
row Ra of bank Ba, and the bank contains a row other than Ra.
In this case, write data may not be directly written into the sense amp array for the bank. It is necessary to close the present row
(precharge) and access the requested row (activate). A precharge command (PRE to bank Ba) is presented on edge T₀. An activate
command (ACT to row Ra of bank Ba) is presented on edge T₆ a time t_RP later. A COL packet with WR command to column Ca1 of bank
Ba is presented on edge T₇ a time t_RCD-W later. A second COL packet with WR command to column Ca2 of bank Ba is presented on
edge T₉. Two write data packets D(a1) and D(a2) follow these COL packets after the write data delay t_CWD. The two COL packets are
separated by the column-cycle time t_CC. This is also the length of each write data packet.
The third timing diagram shows an example of a page-empty wirte transaction. In this case, the selected bank is already closed (no row
is present in the sense amp array for the bank). No row comparison is necessary for this case; however, the memory controller must still
remember that bank Ba has been left closed. In this example, the access is made to row Ra of bank Ba.
In this case, write data may not be directly written into the sense amp array for the bank. It is necessary to access the requested row
(activate). An activate command (ACT to row Ra of bank Ba) is presented on edge T0. A COL packet with WR command to column Ca1
of bank Ba is presented on edge T₁ a time t_RCD-W later. A second COL packet with WR command to column Ca2 of bank Ba is presented
on edge T₃. Two write data packets D(a1) and D(a2) follow these COL packets after the write data delay t_CWD. The two COL packets are
separated by the column-cycle time t_CC. This is also the length of each write data packet. After the final write command, it may be neces-
sary to close the present row (precharge). A precharge command (PRE to bank Ba) is presented on edge T₁₄ a time t_WRP after the last
COL packet with a WR command. The decision whether to close the bank or leave it open is made by memory controller and its page
policy.
The fourth timing diagram shows another example of a page-empty write transaction. This is similar to the previous example except that
only a single write command is presented, rather than two write commands. This example shows that even with a minimum length write
transaction, t_RAS parameter will not be a constraint. The t_RAS measures the minimum time between an activate command and a
precharge command to a bank. This time interval is also constrained by the sum t_RCD-W + t_WRP which will be larger for a write transac-
tion. These two constraints (t_RAS and t_RCD-W + t_WRP) will be a function of the memory device’s speed bin and the data transfer length (the
number of write commands issued between the activate and precharge commands), and the t_RAS parameter could become a constraint
for future speed bins. In this example, the sum t_RCD-W + t_WRPs is greater than t_RAS by the amount ∆t_RAS.
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Rev. 1.1 August 2006