K4Y50164UC Datasheet, PDF (53/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
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K4Y50044UC
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XDR^TM DRAM
11.2 Multiple Bank sets and the ERAW Feature
Figure 54 shows a block diagram of a XDR DRAM in which the banks are divided into two sets (called the even bank set and the odd
bank set) according to the least-significant bit of the bank address field. This XDR DRAM supports a feature called “Early Read After
Write” (hereafter called “ERAW”)
The logic that accepts commands on the RQ11...0 signals is capable of operating these two bank sets independently. In addition, each
bank set connects to its own internal “S” data bus (called S0 and S1). The receive interface is able to drive write data onto either of these
internal data buses, and the transmit interface is able to sample read data from either of these internal data buses. These capabilities will
permit the delay between a write column operation and a read column operation to be reduced, thereby improving performance.
Figure 52 shows the timing previously presented in Figure12, but with the activity on the internal S data bus included. The write-to-read
parameter t_∆WR ensures that there is adequate turnaround time on the S bus between D (a2) and Q (c1).
When ERAW is supported with odd and even bank sets, the t_∆WR,_MIN parameter must be obeyed when the write and read column oper-
ations are to the same bank set, but a second parameter t_∆WR-D permits earlier column operations to the opposite bank set. Figure 53
shows how this is possible because there are two internal data buses S0 and S1. In this example, the four columns read operations are
made to the same bank Bb, but they could use different banks as long as they all belonged to the bank set that was different form the
bank set containing Ba (for the column write operations).
Figure 52 : Write/Read Interaction - No ERAW Feature
CFM
CFMN
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
RQ11..0
WR
a1
WR
a2
t_∆WR
RD
RD
c1
c2 _tCAC
t_CYCLE
DQ15..0
DQN15..0
S[15:0]
[15:0]
D(a1)
t_CWD
D(a2)
t_CC
D(a1)
t_{WR-BUB,XDRDRAM}
turnaround
D(a2)
Q(c1)
Q(c1)
Q(c2)
Q(c2)
t_CC
Transaction a: WR
Transaction c: RD
a1 = {Ba,Ca1}
c1 = {Bc,Cc1}
a2 = {Ba,Ca2}
c2 = {Bc,Cc2}
Figure 53 : Write/Read Interaction - ERAW Feature
CFM
CFMN
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
RQ11..0
DQ15..0
DQN15..0
S0[15:0]
[15:0]
WR
WR
a1
a2
t_∆WR-D
RD
RD
RD
RD
RD
b1 _tCAC b2
b3
b4
c1
D(a1)
t_CWD
D(a2)
Q(b1)
Q(b2)
Q(b3)
t ^tCC _{WR-BUB,XDRDRAM}
turnaround
D(a1)
D(a2)
Q(b4)
Q(c1)
Q(c1)
t_CYCLE
t_CC
S1[15:0]
[15:0]
Q(b1)
Q(b2)
Q(b3)
Q(b4)
Bank Restrictions
Bb is in different bank set than Ba
Bc is in same bank set as Ba
Transaction a: WR
Transaction b: RD
Transaction c: RD
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
c1 = {Bc,Cc1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
b3 = {Bb,Cb3} b4 = {Bb,Cb4}
53 of 76
Rev. 1.1 August 2006