K4Y50164UC Datasheet, PDF (60/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
13.3 Timing Characteristics
Table 17 summarizes all timing parameters that characterize this memory component. The only exceptions are the core timing parame-
ters that are speed-bin dependent. Refer to the Timing Parameters section for more information.
The first section of parameters pertains to the timing of the DQ pins when driving read data.
The second section of parameters is concerned with the timing for the serial interface signals when driving register read data.
The third section of parameters is concerned with the time intervals needed by the interface to transition between power states.
Table 17 : Timing Characteristics
Symbol
Parameter and Other Conditions
Minimum Maximum
t_Q,DQ
t_QOFF,DQ
t_OR,DQ, t_OF,DQ
t_Q,SI
t_P,SI
t_OR,SI, t_OF,SI
t_PDN-ENTRY
t_PDN-EXIT
DRSL DQ output delay (variation across 16 Q bits on each DQ
pin) from drive points - output delay
@ 2.50 ns > t_CYCLE ≥ 2.00 ns
@ 3.33 ns > t_CYCLE ≥ 2.50 ns
@ 3.83 ns ≥ t_CYCLE ≥ 3.33 ns
DRSL DQ output delay offset (a fixed value for all 16 Q bits on
each DQ pin) from drive points - output delay
DRSL DQ output - rise and fall times (20%-80%).
Serial SCK-to-SDO output delay @ C_LOAD,MAX = 15 pF
Serial SDI-to-SDO propagation delay @ C_LOAD,MAX = 15 pF
Serial SDO output rise/fall (20%-80%) @ C_LOAD,MAX = 15 pF
Time for power state to change after PDN entry
Time for power state to change after PDN exit
-0.052
-0.065
-0.080
0.00
0.02
2
-
-
-
0
+0.052
+0.065
+0.080
+0.20
0.04
15
15
10
16
-
Units
ns
ns
ns
t_CYCLE
t_CYCLE
ns
ns
ns
t_CYCLE
t_CYCLE
Figure(s)
Figure 60
Figure 60
Figure 60
Figure 62
Figure 62
Figure 62
Figure 46
Figure 46
60 of 76
Rev. 1.1 August 2006