K4Y50164UC Datasheet, PDF (32/76 Pages) Samsung semiconductor – 512Mbit XDR TM DRAM(C-die)

K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
XDR^TM DRAM
8.5 Propagation Delay
Figure 13 shows two timing diagrams that display the system-level timing relationships between the memory component and the
memory controller.
The timing diagram at the top of the figure shows the case of a write-read-write command and data at the memory component. In this
case, the timing will be identical to what has already been shown in the previous sections; i,e. with all timing measured at the pins of the
memory component. This timing diagram was produced by merging portions of the top and bottom timing diagrams in Figure12.
The example shown is that of a single COL packet with a write command, followed by a single COL packet with a read command,
followed by a second COL packet with a write command. These accesses all assume a page-hit to an open bank.
A timing interval t_∆WR is required between the first WR command and the RD command, and a timing interval t_∆RW is required between
the RD command and the second WR command. There is a write data delay t_CWD between each WR command and the associated write
data packet D. There is a read data delay t_CAC between the RD command and the associated read data packet Q. In this example, all
timing parameters have assumed their minimum values except t_WR-BUB, _XDRDRAM.
The lower timing diagram in the figure shows the case where timing skew is present between the memory controller and the memory
component. This skew is the result of the propagation delay of signal wavefronts on the wire carrying the signals.
The example in the lower diagram assumes that there is a propagation delay of t_PD-RQ along both the RQ wires and the CFM/CFMN
clock wires between the memory controller and the memory component (the value of t_PD-RQ used here is 1*t_CYCLE). Note that in an
actual system the t_PD-RQ value will be different for each memory component connected to the RQ wires.
In addition, it is assumed that there is a propagation delay t_PD-D along the DQ/DQN wires between the memory controller and the
memory component (the direction in which write data travels, and it is assumed that there is the same propagation delay t_PD-Q along the
DQ/DQN wires between the memory component and the memory controller (the direction in which read data travels). The sum of these
two propagation delays is also denoted by the timing parameter t_PD,CYC = t_PD-D + t_PD-Q.
As a result of these propagation delays, the position of packets will have timing skews that depend upon whether they are measured at
the pins of the memory controller or the pins of memory component. For example, the CFM/CFMN signals at the points of the memory
component are t_PD-RQ later than at the pins of the memory controller. This is shown by the cycle numbering of the CFM/CFMN signals at
the two locations - in this example cycle T₁ at the memory controller aligns with cycle T₀ at the memory component.
All the request packets on the RQ wires will have a t_PD-RQ skew at the memory component relative to the memory controller in this
example. Because the t_PD-D propagation delay of write data matches the t_PD-RQ propagation delay of the write command, the controller
may issue the write data packet D(a0) relative to the COL packet with the first write command “WR(a0)” with normal write data delay
t_CWD. If the propagation delays between the memory controller and memory component were different for the RQ and DQ buses (not
shown in this example), the write data delay at the memory controller would need to be adjusted.
A propagation delay is seen by the read command - that is, the read command will be delayed by a t_PD-RQ skew at the memory compo-
nent relative to the memory controller. The memory componet will return the read data packet Q(b0) relative to this read command with
the normal read data delay t_CAC (at the pins of the memory componet).
The read data packet will be skewed by an additional propagation delay of t_PD-Q as it travels from the memory component back to the
memory controller. The effective read data delay measured between the read command and the read data at the memory controller will
be t_CAC + t_PD-RQ + t_PD-Q.
t_PD-RQ factor is casued by the propagaion delay of the request packets as they travel from memory controller to memory component. The
t_PD-Q factor is casued by the propagation delay of the read data packets as they travel from memory componet to memory controller.
All timing parameters will be equal to their minimum values except t_WR-BUB,_XDRDRAM (as in the top diagram), and the timing parameters
t_RW-BUB,_XDRDRAM and t_∆RW. These will be larger than their minimum values by the amount (t_PD,_CYC - t_PD,_CYC,_MIN), where t_PD,_CYC = t_PD-
D ^{+ t}PD-Q^{. This may be seen by evaluating the two timing paths between cycle T}9 ^{at th controller and cycle T}21 ^{at the XDR DRAM:}
t_∆RW + t_PD-RQ + t_CWD = t_PD-RQ + t_CAC + t_CC + t_RW-BUB,_XDRDRAM or t_∆RW = (t_CAC - t_CWD) + t_CC + t_{RW-BUB,XDRDRAM}
The following relationship was shown for Figure12.
t_∆RW, _MIN = (t_CAC - t_CWD) + t_CC + t_RW-BUB, _{XDRDRAM, MIN} or (t_∆RW - t_∆RW, _MIN) = (t_RW-BUB, _XDRDRAM - t_{RW-BUB, XDRDRAM}, _MIN)
In other words, the two timing parameters t_RW-BUB,_XDRDRAM and t_∆RW will change together. The relationship of this change to the propa-
gation delay t_PD,_CYC (=t_PD-D + t_PD-Q) can be derived by looking at the two timing paths from T₁₅ to T₂₁ at the XDR DRAM:
t_PD-Q + t_CC + t_RW-BUB,_XIO + t_PD-D = t_CC + t_{RW-BUB,XDRDRAM} or t_RW-BUB,_XDRDRAM = t_RW-BUB,_XIO + t_PD-D + t_PD-Q or t_RW-BUB,_XDRDRAM = t_RW-
BUB^,XIO ^{+ t}PD^,CYC
In a system with minimum propagation delays: t_RW-BUB,_XDRDRAM,_MIN = t_RW-BUB,_XIO + t_PD,_CYC,MIN
and since t_RW-BUB,_XIO is equal to t_RW-BUB,_XIO,_MIN in the both cases, the following is true: (t_PD,_CYC - t_PD,_CYC,_MIN) = (t_RW-BUB,_XDRDRAM -
t_RW-BUB,_XDRDRAM,_MIN) = (t_∆RW - t_∆RW,_MIN)
In other words, the values of the t_RW-BUB,_XDRDRAM,_MIN and t_∆RW,MIN timing parameters correspond to the value of t_PD,_CYC,_MIN for the
system (this is equal to one t_CYCLE). As t_PD,_CYC is increased from this minimum value, t_RW-BUB,_XDRDRAM and t_∆RW increase from their
minimum values by an equivalent amount.
32 of 76
Rev. 1.1 August 2006